FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 135
FX3 P-Port Register Access
10.2.4 PP_INTR_MASK Register
P-port Interrupt Mask register. This register has the same layout as PP_EVENT register and mask
which event lead to assertion of INTR.
10.2.5 PP_DRQR5_MASK
P-Port DRQ/R5 Mask Register. This register has the same layout as PP_EVENT and mask which
events lead to assertion of INTR or DRQ/R5 respectively. DRQR5 is a signal that can be put on any
GPIF CTRL[x] line (see GPIF_BUS_SELECT).
10.2.6 PP_SOCK_MASK
P-Port Socket Mask Register. This registers contain a mask that indicates which sockets affect the
SOCK_AGG_A and SOCK_AGG_B values respectively.
Bits Name HW SW Default Description
0 SOCK_AGG_AL R RW 0 1: Forward EVENT onto INT line
1 SOCK_AGG_AH R RW 0 1: Forward EVENT onto INT line
2 SOCK_AGG_BL R RW 0 1: Forward EVENT onto INT line
3 SOCK_AGG_BH R RW 0 1: Forward EVENT onto INT line
4 GPIF_INT R RW 0 1: Forward EVENT onto INT line
5 PIB_ERR R RW 0 1: Forward EVENT onto INT line
6 MMC_ERR R RW 0 1: Forward EVENT onto INT line
7 GPIF_ERR R RW 0 1: Forward EVENT onto INT line
11 DMA_WMARK_EV R RW 0 1: Forward EVENT onto INT line
12 DMA_READY_EV R RW 0 1: Forward EVENT onto INT line
13 RD_MB_FULL R RW 1 1: Forward EVENT onto INT line
14 WR_MB_EMPTY R RW 0 1: Forward EVENT onto INT line
15 WAKEUP R RW 0 1: Forward EVENT onto INT line
Bits Name HW SW Default Description
0 SOCK_AGG_AL R RW 0 1: Forward EVENT onto DRQ line
1 SOCK_AGG_AH R RW 0 1: Forward EVENT onto DRQ line
2 SOCK_AGG_BL R RW 0 1: Forward EVENT onto DRQ line
3 SOCK_AGG_BH R RW 0 1: Forward EVENT onto DRQ line
4 GPIF_INT R RW 0 1: Forward EVENT onto DRQ line
5 PIB_ERR R RW 0 1: Forward EVENT onto DRQ line
6 MMC_ERR R RW 0 1: Forward EVENT onto DRQ line
7 GPIF_ERR R RW 0 1: Forward EVENT onto DRQ line
11 DMA_WMARK_EV R RW 0 1: Forward EVENT onto DRQ line
12 DMA_READY_EV R RW 0 1: Forward EVENT onto DRQ line
13 RD_MB_FULL R RW 1 1: Forward EVENT onto DRQ line
14 WR_MB_EMPTY R RW 0 1: Forward EVENT onto DRQ line
15 WAKEUP R RW 0 1: Forward EVENT onto DRQ line
Bits Name HW SW Default Description
31:0 SOCK_MASK R RW 0
For socket <x>, bit <x> indicates:
0: Socket does not affect SOCK_AGG_A/B
1: Socket does affect SOCK_AGG_A/B