128 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
Table 9-3. Complex GPIO Registers
9.3.1 PIN_STATUS Register
This register controls mode of operation and configuration for a single complex I/O pin. It also
reflects the current I/O status. This register is valid only for complex GPIO.
Offset Width Name Description
0xE0001000 +
(GPIO_ID MOD
8) * 0x10
32 PIN_STATUS Configuration, mode and status of I/O Pin.
0xE0001004 +
(GPIO_ID MOD
8) * 0x10
32 PIN_TIMER Timer/counter for pulse and measurement modes.
0xE0001008 +
(GPIO_ID MOD
8) * 0x10
32 PIN_PERIOD Period length for revolving counter / timer (GPIO_TIMER).
0xE000100C +
(GPIO_ID MOD
8) * 0x10
32 PIN_THRESHOLD Threshold for measurement register.
Bits Name HW SW Default Description
0 OUT_VALUE RW RW 1
Output value used for output drive (if DRIVE_EN=1)
0: Driven Low
1: Driven High
1IN_VALUE W R 0
Present input measurement
0: Low
1: High
4
DRIVE_LO_
EN
RRW 0
Output driver enable when OUT_VALUE=0
0: Output driver is tri-stated
1: Output-driver is active (weak/strong is determined in
I/O Matrix)
5
DRIVE_HI_E
N
RRW 0
Output driver enable when OUT_VALUE=1
0: Output driver is tri-stated
1: Output-driver is active (weak/strong is determined in
I/O Matrix)
6 INPUT_EN R RW 0
0: Input stage is disabled
1: Input stage is enabled, value is readable in IN_VALUE
To Next Page
Loading...