Cypress EX-USB FX3 - Long Transfer - Integral Number of Buffers

FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 143
FX3 P-Port Register Access
The AP can observe the completion of a ZLB transfer by polling the DMA_XFER register. This
should not take more than a couple of cycles.
Figure 10-5. Zero Length Read (Egress) Transfer
Figure 10-6. Zero Length Write (Ingress) Transfer
The following should be noted:
For read transfers, DMA_ENABLE de-asserts shortly after a DMA_XFER read with SIZE_VALID=1.
For write transfers, all signals de-assert shortly after the write of DMA_SIZE=0.
10.4.5 Long Transfer – Integral Number of Buffers
A long transfer is coordinated between AP and Benicia CPU using a higher layer protocol, e.g. built
on mailbox messaging. The length of transfer is conveyed to Benicia CPU which configures buffers
and sockets required for transfer.
The following diagram illustrates the long transfer:
SIZEEVENT
SOC K _
STAT _X
DMA_WMARK
SOCK_STAT[N]
A/D
R/W#
DMA_
XFER
DMA_ENABLE
DMA_READY
DMA_
XFER
EVENT
SOCK _
STAT _ X
DMA_WMARK
SOCK_STAT[N]
A/D
R/W#
SIZE
DMA_
XFER
DMA_ENABLE
DMA_READY
DMA_
XFER
DMA_
XFER