136 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 P-Port Register Access
10.2.7 PP_ERROR
P-Port Error Indicator Register. This register indicates the error codes associated with
PIB_INTR.PIB_ERR, MMC_ERR and GPIF_ERR. The different values for these error codes will be
documented in the P-Port BROS document. This register is also visible to firmware as PIB_ERROR.
10.2.8 PP_DMA_XFER
P-Port DMA Transfer Register. This register is used to setup and control a DMA transfer.
Bits Name HW SW Default Description
5:0 PIB_ERR_CODE RW R 0 Mirror of corresponding field in PIB_ERROR
9:6 MMC_ERR_CODE RW R 0 Mirror of corresponding field in PIB_ERROR
14:10 GPIF_ERR_CODE RW R 0 Mirror of corresponding field in PIB_ERROR
Bits Name HW SW Default Description
7:0 DMA_SOCK R RW 0
Processor specified socket number for data
transfer
8 DMA_ENABLE RW RW 0
0: Disable ongoing transfer. If no transfer is
ongoing ignore disable
1: Enable data transfer
9 DMA_DIRECTION R RW 0
0: Read (Transfer from Bay – Egress direc-
tion)
1: Write (Transfer to Bay – Ingress direction)
10 LONG_TRANSFER R RW 0
0: Short Transfer (DMA_ENABLE clears at
end of buffer
1: Long Transfer (DMA_ENABLE must be
cleared by AP at end of transfer)
12 SIZE_VALID RW R 0
Indicates that DMA_SIZE value is valid and
corresponds to the socket selected in
PP_DMA_XFER. SIZE_VALID will be 0 for
a short period after PP_DMA_XFER is writ-
ten into. AP polls SIZE_VALID or
DMA_READY before reading DMA_SIZE
13 DMA_BUSY W R 0
Indicates that link controller is busy process-
ing a transfer. A zero length transfer would
cause DMA_READY to never assert.
0: No DMA is in progress
1: DMA is busy
14 DMA_ERROR W R 0
0: No errors
1: DMA transfer error
This bit is set when a DMA error occurs and
cleared when the next transfer is started
using DMA_ENABLE=1.
15 DMA_READY W R 0
Indicates that the link controller is ready to
exchange data.
0: Socket not ready for transfer
1: Socket ready for transfer; SIZE_VALID is
also guaranteed 1
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