FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 33
FX3 Overview
capture data on the asserting edge of the clock and transmit at the de-asserting edge. When Idle,
the SCLK pin remains de-asserted. Hence, the first toggle of SCLK in this mode (CPHA=0) will
cause the receivers to latch data; placing a constraint on the transmitters to set up data before the
first toggle of SCLK. To SSN LEAD setting is provided to facilitate the assertion of SS (and hence the
first transmit data) a few cycles before the first SCLK toggle. The SSN LAG setting specifies the
delay in SSN de-assertion after the last SCLK toggle for the transfer. This specific mode of operation
(CPHA=0) also necessitate toggling the SSN signal between word transfers.
The SSN pin can be configured to either remain asserted always, deassert between transfers,
handled by hardware (based on CPHA configuration) or managed using software. FX3's SPI block
can share its MOSI, MISO, and SCLK pins with more than one slave connected on the bus. In this
case, the SSN signal of the block cannot be used and the slave selects need to be managed using
GPIOs.
3.6.5 GPIO/Pins
Several pins of FX3 can function as General Purpose IO s. Each of these pins is multiplexed to
support other functions / interfaces (like UART, SPI and so on). By default, pins are allocated in
larger groups to either one block or the other (Blk IO) depending on the interface mode in their
respective power domain. In a typical application, not all blocks of FX3 are used. Even so, not all
pins of blocks being used are utilized. Unused pins in each block may be overridden as a simple or
complex GPIO pin on a pin-by-pin basis.
Simple GPIO provides software controlled and observable input and output capability only. In
addition, they can also raise interrupts. Complex GPIOs add 3 timer/counter registers for each and
support a variety of time based functions. They either work off a slow or fast clock. Complex GPIOs
can also be used as general purpose timers by firmware.
There are eight complex IO pin groups, the elements of which are chosen in a modulo 8 fashion
(complex IO group 0 – GPIO 0, 8, 16., complex IO group 1- GPIO 1,9,17., and so on). Each group
can have different complex IO functions (like PWM, one shot and so on). However, only one pin from
a group can use the complex IO functions. The rest of the pins in the group are either used as block
IO or simple GPIO.
The tables below illustrate the IO Matrix in FX3.
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