32 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Overview
3.6.4 SPI
Figure 3-9. SPI Block Diagram
FX3's SPI block operates in master mode and facilitates standard full-duplex synchronous transfers
using the MOSI (Master out Slave In), MISO (Master In Slave Out), SCLK (Serial Clock), and SS
(Slave select) pins. The maximum frequency of operation is 33 MHz. Similar to the I2S and I
2
C and
UART blocks, this block supports both single and burst (DMA) data transfers.
The transmit and receive blocks can be enabled independently using the TX_ENABLE/RX_ENABLE
inputs. Independent shift registers are used for the transmit and receive paths. The width of the shift
registers can be set to anywhere between 4 and 32 bits. By default, the Tx and Rx registers shift
data to the left (big endian). This can be reversed, if necessary.
The SSPOL input sets the polarity of the SSN (Slave Select) signal.The CPOL input sets the polarity
of the SCLK pin which is active high by default. The CPHA input sets the clock phases for data
transmit and capture. If CPHA is set to ‘1’, the devices agree to transmit data on the asserting edge
of the clock and capture at the de-asserting edge. However, if CPHA is set to 0, the devices agree to
N
N-1
N-2
10
TX - SHIFT
REGISTER
RX - SHIFT
REGISTER
N
N-1
N-2
10
SHIFT REGISTER
SCLK
SSN
FX3 SPI
MASTER
SPI SLAVE
MOSI
MISO
N
N-1
N-2
10
ENDIAN
ENDIAN
ENABLE
RX_ENABLE
TX_ENABLE
LOOPBACK
ENDIAN
CONTROL
CPOL
CPHA
SSNCTRL
FW_SSN
SSN_DESELECT
SS_POL
LEAD
LAG
WID_SEL (N+1)
CLK
DMA/SGL TRANSFER
SGL_TX_DATA
SGL_RX_DATA
DMA_TX_DATA
DMA_RX_DATA
TX_BYTE_COUNT
RX_BYTE_COUNT
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