126 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
9.2.2 GPIO_SIMPLE Register
This register controls mode of operation and configuration for a single I/O Pin. It also exposes status
and read value. There are 61 registers, one for each GPIO. This register is valid only for the I/Os
configured as simple GPIO.
9.2.3 GPIO_INVALUE0 Register
Input state of the GPIO 0-31. Each bit indicates the state of GPIO.
Bits Name HW SW Default Description
0 OUT_VALUE R RW 1
Output value used for output drive (if DRIVE_EN=1)
0: Driven Low
1: Driven High
1IN_VALUEWR 0
Present input measurement
0: Low
1: High
4 DRIVE_LO_EN R RW 0
Output driver enable when OUT_VALUE=0
0: Output driver is tristated
1: Output-driver is active (weak/strong is determined in IO
Matrix)
5 DRIVE_HI_EN R RW 0
Output driver enable when OUT_VALUE=1
0: Output driver is tristated
1: Output-driver is active (weak/strong is determined in IO
Matrix)
6 INPUT_EN R RW 0
0: Input stage is disabled
1: Input stage is enabled, value is readable in IN_VALUE
26:24 INTRMODE R RW 0
Interrupt mode
0: No interrupt
1: Interrupt on posedge
2: Interrupt on negedge
3: Interrupt on any edge
4: Interrupt when pin is low
5: Interrupt when pin is high
6-7: Reserved
27 INTR
RW1
S
RW1
C
0
Registers edge triggered interrupt condition. Only relevant
when INTRMODE=1,2,3,6,7. When INTRMODE=4,5 pin
status is fed directly to interrupt controller; condition can be
observed through IN_VALUE in this case.
31 ENABLE R RW 0 Enable GPIO logic for this pin.
Bits Name HW SW Default Description
31:0 INVALUE0 W R 0 If bit <x> is set, state of GPIO <x> is high.
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