FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 27
FX3 Overview
Figure 3-4. Vector Interrupt Controller
When both FIQ and IRQ interrupt inputs assert, the CPU jumps to the FIQ entry of the exception
table. The FIQ handler is usually placed immediately after the table, saving a branch. The FIQ mode
uses dedicated FIQ bank registers. When an IRQ line alone asserts, CPU jumps to the IRQ handler.
The IRQ handler saves the workspace on stack, reads the address of the ISR from the VIC, and
jumps to the actual ISR.
In general, high priority, low latency interrupts are vectored into FIQ while the IRQ line is reserved for
general interrupts. Re-entrant interrupts can be supported with additional firmware.
3.5 JTAG Debugger Interface
Debug support is implemented by using the ARM9EJ-S core embedded within the ARM926EJ-S
processor. The ARM9EJ-S core has hardware that eases debugging at the lowest level. The debug
extensions allow to stall the core's program execution, examine the internal state of the core and the
memory system, and further resume program execution.
Figure 3-5. ARM Debug Logic Blocks
A
H
B
L
O
G
I
C
AHB
Interface
INT_ENABLE/DISABLE[31:0]
INT_SELECT_FIQ_IRQ#[31:0]
INT_PRIORITY[4:0][0:31]
INT_PRIORITY_MASK[15:0]
INT_ADDRESS[31:0][0:31]
IRQ_STATUS[31:0]
FIQ_STATUS[31:0]
Other FIQ int lines
Masking and
Priority logic
PL 192 VIC (Simplified)
Int_line[n]
Int_endis[n]
Int_fiqirq#[n]
Int_priority[4:0][n]
Int_priority_mask
[Int_priority[4:0][n]]
CUR_INT_ADDRESS[31:0]
nFIQ
nIRQ
ARM9EJS
Core
Embedded
ICE-RT
Scan 1
Scan 2
TAP
Controller
Embedded ICE
Debug
Interface
JTAG
Interface
CPU SUBSYSTEM
(Debug logic)
FX3 (Debug logic)
JTAG to USB
Protocol Converter
(ICE box)
Real View
Debugger
PC
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