FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 131
10. FX3 P-Port Register Access
FX3’s processor interface is a General Programmable parallel interface (GPIF) that can be pro-
grammed to operate with:
1. 8 bit address
2. 8, 16 or 32 bit data bus widths
3. Burst sizes: 2 thru 2^14
4. Buffer sizes: 16 * n; for n 1 thru 2048: Max buffer size of 32 KB
5. Buffer switching overhead 550 - 900 ns per buffer
The PP Register protocol enables data transfers between Application Processor and Benicia’s paral-
lel port.
The PP Register protocol uses a special register map of 16-bit registers that can be accessed
through the GPIF interface. These addresses are not accessible internal to the device.
The PP register protocol as seen through GPIF uses the following mechanisms:
P-port addresses in the range 0x80-FF expose a bank of 128 16-bit registers. Some of these regis-
ters are used to implement the mechanisms mentioned below, and others control configuration, sta-
tus and behavior of the P-Port.
Accesses to any address in the range 0x00-7F are used for FIFO-style read or write operations into
the ‘active’ socket (to be explained later).
Special registers implement the ‘mailbox’ protocol. These registers are use to transfer messages of
up to 8-bytes between the Application Processor and the Benicia CPU.
10.1 Glossary
Egress Direction of transfer - out of Benicia to external device
Ingress Direction of transfer – into Benicia from external device
Long transfer DMA transfer spanning multiple buffers
Short transfer DMA transfer spanning one buffer
Full Transfer DMA transfer comprising of full buffer
Partial transfer DMA transfer comprising of less than full buffer
Zero Length
transfer
Transfer of a zero length buffer (packet)
ZLB Zero length buffer
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