Cypress EX-USB FX3 - Odd Sized Transfers; 10 DMA Transfer Signaling on ADMUX Interface

146 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 P-Port Register Access
Figure 10-10. Egress Long Transfer - with Partial Last Buffer
10.4.9 Odd sized transfers
Whenever a packet is transferred that consists of an odd number of bytes, all words transferred are
full words except the last one. The last word will contain only the valid bytes padded with 0. In big
endian mode this will be the MSB in little endian mode this will be the LSB. The other bytes will con-
tain 0 on read and will be ignored on write.
This scheme is independent of how the memory buffer is aligned in memory inside of Benicia (which
is irrelevant to the application processor). In other words the first word of a transfer is always a full
word, even if the buffer is misaligned in internal memory.
10.4.10 DMA transfer signalING on ADMUX interface
The figure illustrates DRQ# signaling on P-port interface for a long transfer. In this figure
DMA_WMARK is mapped to DRQ# signal. Note that DRQ is programmed active-low in this exam-
ple. The buffer-switching time is illustrated as the time from the last data cycle for a buffer to the first
cycle of next buffer.
Figure 10-11. Long Transfer Using DMA_WMARK Mapped to DRQ# Signal
Each burst, Bx, in the figure above is comprises of one address and burst-size data cycles. One
example for a burst-of-16-read on ADMux interface is illustrated in figure below.
Note that the RDY signal shown in figure below is the link level ready signal. This RDY signal is dif-
ferent from the higher level DMA control DMA_READY/DRQ signaling.
DMA_READY
SOCK_STAT[N]
A/D
R/W#
DMA_
XF ER
DMA_ENABLE
DMA_WMARK
N
2
DMA_
XF ER
Buffer 0
Burst 1
Buffer 0
Burst 0
Buffer 0
Burst 3
Buffer 0
Burst 2
Buffer N
Burst 1
Buffer N
Burst 0
0
DRQ #
AQ/DQ[15:0]
B0
B1
Note:
B – Burst – refers to Burst Read or Burst Write
~DMA_WMARK
Buffer-switching time
Bn-2
Bn-1 Bn Bn+1 B2n-2 B2n-