Cypress EX-USB FX3 - Page 147

FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 147
FX3 P-Port Register Access
Figure 10-12. Burst of 16 Read on ADMux Interface
A[0:7]/DQ[0:31]
ADV#
CE#
WE#
tAVWE
tS
Valid
Address
tS
D1
tH
tS tH
tDHtDS
tCLKH tCLKL
tCLK
CLK
D0
RDY
High-Z
tKW
tWZ
tKW
Note:
1. 2-cycle latency is shown .
2. RDY active high shown. RDY can be programmed to either active low or active high.
D2 D14D3 D15
tDH