FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 119
FX3 Serial Peripheral Register Access
9.1.3.11 UART_POWER register
This register is used to power the UART block ON/OFF or to reset the block.
9.1.4 SPI Registers
The SPI block on the FX3 device is a SPI master interface that can be configured with different word
sizes, clock frequencies and modes of operation. While the block automatically supports the use of
default Slave Select (SSN) pin, the firmware can use other GPIOs on the FX3 device to talk to other
slaves.
This section documents the SPI related configuration and status registers.
9.1.4.1 SPI_CONFIG register
This register configures the operating parameters for the SPI interface on the FX3 device.
Bits Field Name
HW
Access
SW
Access
Default Value Description
0ACTIVE W R 0
Indicates whether the block is active.
Will be set to 0 for some time after the
block is reset, and will be set to 1 after
the block has been fully powered up.
31 RESETN R RW 0
Active LOW reset signal for all logic in
the block.
After setting this bit to 1, firmware polls
and waits for the ‘active’ bit to assert.
Assert this bit ('0') for at least 10 µs for
effective block reset.
Name
Width
(bits)
Address Description
SPI_CONFIG 32 0xE0000C00 Configuration and modes register
SPI_STATUS 32 0xE0000C04 Status register
SPI_INTR 32 0xE0000C08 Interrupt status register
SPI_INTR_MASK 32 0xE0000C0C Interrupt mask register
SPI_EGRESS_DATA 32 0xE0000C10 Write data register
SPI_INGRESS_DATA 32 0xE0000C14 Read data register
SPI_SOCKET 32 0xE0000C18 Socket select register
SPI_RX_BYTE_COUNT 32 0xE0000C1C Receive byte count register
SPI_TX_BYTE_COUNT 32 0xE0000C20 Transmit byte count register
SPI_ID 32 0xE0000FF0 Block ID register
SPI_POWER 32 0xE0000FF4 Power and reset register
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_ENABLE R RW 0
0: Receiver disabled, ignore incoming data
1: Receiver enabled
1 TX_ENABLE R RW 1
0: Transmitter disable, do not transmit data
1: Transmitter enabled
2DMA_MODER RW0
0: Register-based transfers
1: DMA-based transfers
3 ENDIAN R RW 0
0: Transfer MSB First
1: Transfer LSB First
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