118 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
9.1.3.7 UART_SOCKET register
This register is used to select the LPP DMA sockets through which the UART block will send or
receive data.
9.1.3.8 UART_RX_BYTE_COUNT register
This register specifies the length of data to be received through the UART interface. This register is
only relevant in DMA mode of transfer, and will be continually decremented by the UART block while
data transfer is ongoing. Once this counter reaches zero, the UART_STATUS.RX_DONE bit will be
set.
9.1.3.9 UART_TX_BYTE_COUNT register
This register specifies the length of data to be transmitted through the UART interfaces, and is rele-
vant only in DMA mode. The counter will be decremented by the UART block as it is transmitting
data; and the TX_DONE status will be set when the count reaches zero.
9.1.3.10 UART_ID register
The block ID register is a read-only register that allows the CPU to identify whether the UART block
is powered on.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
7:0 EGRESS_SOCKET R RW 0
Socket number for egress data
0 - 7: Supported
This field should be set to 3.
15:8 INGRESS_SOCKET R RW 0
Socket number for ingress data
0 - 7: Supported
This field should be set to 6.
Bits Field Name
HW
Access
SW
Access
Default Value Description
31:0 BYTE_COUNT RW RW 0xFFFFFFFF
Number of bytes left to receive.
0xFFFFFFFF indicates infinite trans-
fer (counter will not decrement).
Bits Field Name
HW
Access
SW
Access
Default Value Description
31:0 BYTE_COUNT RW RW 0xFFFFFFFF
Number of bytes left to transmit.
0xFFFFFFFF indicates infinite trans-
fer (counter will not decrement).
Bits Field Name
HW
Access
SW
Access
Default Value Description
15:0 BLOCK_ID R 0x0002
A unique number identifying the
block in the memory space.
31:16 BLOCK_VERSION R 0x0001 Version number for the block.
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