134 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 P-Port Register Access
10.2.3 PP_CONFIG Register
P-Port Configuration Register. This register contains various P-Port configuration options. Many of
these values need to be interpreted by firmware and converted into relevant GPIF setting changes.
No direct hardware effects are implemented except where stated otherwise below. Writing to this
register will lead to a firmware interrupt PIB_INTR.CONFIG_CHANGE.
Bits Name HW SW Default Description
3:0 BURSTSIZE R RW 15
Size of DMA bursts; only relevant when
DRQMODE=1.
0-14: DMA burst size is 2BURSTSIZE words
15: DMA burst size is infinite (DRQ de-
asserts on last cycle of transfer)
6 CFGMODE RW RW 1
Initialization Mode
0: Normal operation mode.
1: Initialization mode.
This bit is cleared to “0” by firmware, by writ-
ing 0 to PIB_CONFIG.PP_CFGMODE, after
completing the initialization process. Specific
usage of this bit is described in the software
architecure. This bit is mirrored directly by
HW in PIB_CONFIG.
7 DRQMODE R RW 0
DMA signaling mode. See DMA section for
more information.
0: Pulse mode, DRQ will de-assert when
DACK de-asserts and will remain de-
asserted for a specified time (see EROS).
After that DRQ may re-assert depending on
other settings.
1: Burst mode, DRQ will de-assert when
BURSTSIZE words are transferred and will
not re-assert until DACK is de-asserted.
9 INTR_OVERRIDE R RW 0
0: No override
1: INTR signal is forced to INTR_VALUE
This bit is used directly in HW to generate
INT signal.
10 INTR_VALUE R RW 0
0: INTR is de-asserted when
INTR_OVERRIDE=1
1: INTR is asserted on override when
INTR_OVERRIDE=1
This bit is used directly in HW to generate
INT signal.
11 INTR_POLARITY R RW 0
0: INTR is active low
1: INTR is active high
This bit is used directly in HW to generate
INT signal.
12 DRQ_OVERRIDE R RW 0
0: No override
1: DRQ signal is forced to DRQ_VALUE
13 DRQ_VALUE R RW 0
0: DRQ is de-asserted when
DRQ_OVERRIDE=1
1: DRQ is asserted when
DRQ_OVERRIDE=1
14 DRQ_POLARITY R RW 0
0: DRQ is active low
1: DRQ is active high
15 DACK_POLARITY R RW 0
0: DACK is active low
1: DACK is active high
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