FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 141
FX3 P-Port Register Access
Figure 10-2. Short Transfer - DMA Transfer Sequence
10.4.3 Short Transfer – Partial Buffer
A partial write (ingress) transfer is defined as a transfer that writes fewer bytes than the available
space in the buffer.
A partial read (egress) transfer is defined as a transfer that transfers less than the number of bytes
available in the current buffer.
The normal mechanism for a partial transfer is to write the number of bytes to transfer into
DMA_SIZE. This can be done only after a DMA_XFER.SIZE_VALID asserted. It is also possible to
explicitly terminate a transfer by clearing DMA_ENABLE in DMA_XFER. Note that in that case, it is
not possible to transfer an odd number of bytes.
Application
Processor
GPMC port
Benicia
P-port
AP gets interrrupted by
INTR#. AP reads
PP_SOCK_STAT and
determins sockets ready
for transfer.
SOCK_STAT[N],
DMA_READY,
DMA_ENABLE all become
zero
AP polls for DMA_READY
Processor writes
DMA_XFER with socket -
number, direction and
DMA_ENABLE=1.
SOCKET N has a
empty (full) buffer
that causes
PP_SOCK_STAT[N]
to be set.
AP optionally polls
PP_DMA_XFER for
SIZE_VALID to become 1,
if PP_DMA_SIZE is
required to write (read).
AP may optionally set
PP_DMA_SIZE for short
transfers
AP configures
PP_DRQR5_MASK to
assign DMA_WMARK_EV
to DRQ signal.
AP starts bursting data
from (to) socket
Data produced
(consumed) on
socket N makes
filled (empty) buffer
available to other
peripherals or CPU.
DMA_WMARK_EV
deasserts indicating that
AP should stop/pause
bursting.
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