Cypress EX-USB FX3 - 5. FX3 Firmware; 5.1 Initialization

FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 53
5. FX3 Firmware
The chapter presents the programmers overview of the FX3 device. The boot and the initialization
sequence of the FX3 device is described. This sequence is handled by the firmware framework. A
high level overview of the API library is also presented, with a description of each programmable
block.
5.1 Initialization
The system initialization sequence sets up the CPU sub-system, initializes the firmware framework,
and sets up other modules of the firmware framework. It is the initialization point for the RTOS.
The following high level activities are handled as part of the initialization sequence.
■ Device configuration: The type of device is identified by reading the eFuse registers or the
PMODE pins. The FX3 boot mode and GPIF startup I/O interface configuration is determined by
the PMODE pins. The I/O ports (USB, GPIF, and serial interfaces) are set up according to the
device type and the internal I/O matrix is configured accordingly.
■ Clock setup: The firmware framework sets the CPU clock at startup.
■ MMU and cache management: The FX3 device does not support virtual memory. The FX3
device memory is a one to one mapping from virtual to physical addresses. This is configured in
the MMU. The device MMU is enabled to allow the use of the caches in the system. By default,
the caches are disabled and invalidated on initializing the MMU.
■ Stack initialization: The stacks needed for all modes of operation for the ARM CPU (System,
Supervisor, FIQ, IRQ) are set up by the system module.
For all user threads, the required stack space must be allocated prior to thread creation. Separate
APIs are provided to create a runtime heap and to allocate space from the heap.
■ Interrupt management: The FX3 device has a vectored interrupt controller. Exception vectors
and VIC are both initialized by this module. The exception vectors are in the I-TCM and are
located from address 0x0 (refer to memory map).
The actual initialization sequence is shown in the following figure.