120 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
4 SSN_BIT R RW 0
This bit controls SSN behavior at the end of
each received and transmitted word, if SSNC-
TRL indicates firmware SSN control.
This bit is transmitted over SSN line “as is”,
without regards to how many cycles it is going
out.
SSPOL is applied. The FW is expected to
send one word at a time in this mode. DESE-
LECT bit takes precedence over this bit.
Typically the FW shall keep this bit asserted
for the entire transaction that can span multiple
words.
Modify only when ENABLE=0.
5 LOOPBACK R RW 0
0: No effect
1: Send the value being transmitted to the
receive buffer. Disable external transmit and
receive.
9:8 SSNCTRL R RW 1
00: SSN is toggled by FW.
01: SSN remains asserted between each 8-bit
transfer.
10: SSN asserts high at the end of the transfer.
11: SSN is governed by CPHA
10 CPOL R RW 0
0: SCK idles low
1: SCK idles high
11 CPHA R RW 0 Transaction start mode.
13:12 LEAD R RW 1
SSN-SCK lead time. Indicates the number of
half-clock cycles SSN need to assert ahead of
the first SCK cycle.
00: Reserved
01: 0.5 SCK cycles
10: 1 SCK cycle
11: 1.5 SCK cycles
15:14 LAG R RW 1
SCK-SSN lag time. Indicates the number of
half-clock cycles for which SSN needs to
remain asserted after the last SCK cycle
including zero.
Note that LAG must be > 0 when CPHA=1.
16 SSPOL R RW 0 0: SSN is active low, else active high.
22:17 WL R RW 8
SPI transaction unit length.
Can take values from 4 to 32.
0 - 3 are reserved.
23 DESELECT R RW 0
1: Never assert SSN. Used to direct SPI traffic
to non-default slaves whose SSN are con-
nected to GPIO.
0: Normal SSN behavior.
29 RX_CLEAR R RW 0
0: Do nothing
1: Clear receive FIFO
Firmware must wait for RX_DATA=0 before
clearing this bit again.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
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