FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 121
FX3 Serial Peripheral Register Access
9.1.4.2 SPI_STATUS register
30 TX_CLEAR R RW 0
0: Do nothing
1: Clear transmit FIFO
Firmware must wait for TX_DONE before
clearing this bit.
31 ENABLE R RW 0
Enable block here, but only after all of the con-
figuration is set. Do not set this bit to 1 while
changing any other value in this register.
Setting this bit to 0 will complete transmission
of current sample. When DMA_MODE = 1,
any remaining samples in the pipeline are dis-
carded. When DMA_MODE = 0, no samples
are lost.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_DONE W R 0
Indicates receive operation completed.
Non sticky
Only relevant when DMA_MODE=1.
Receive operation is complete when transfer
size bytes in socket have been received.
1RX_DATA W R 0
Indicates data is available in the RX FIFO.
Non sticky.
Only relevant when DMA_MODE=0.
This bit is updated immediately after reads
from INGRESS_DATA register.
2RX_HALF W R 0
Indicates that the RX FIFO is at least half full.
Non sticky.
Only relevant when DMA_MODE=0.
This bit is updated immediately after reads
from INGRESS_DATA register.
3TX_DONE W R 0
Indicates no more data is available for trans-
mission.
Non sticky.
If DMA_MODE=0, this is defined as TX FIFO
empty and shift register empty. If
DMA_MODE=1, this is defined as
BYTE_COUNT=0 and shift register empty.
4 TX_SPACE W R 1
Indicates space is available in the TX FIFO.
Non sticky
This bit is updated immediately after writes to
EGRESS_DATA register.
5TX_HALF W R 1
Indicates that the TX FIFO is at least half
empty.
Non sticky
This bit is updated immediately after writes to
EGRESS_DATA register.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
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