FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 100
FX3 Serial Peripheral Register Access
3WSMODER RW0
I2S_MODE:
0: WS = 0 denotes the left Channel
1: WS = 0 denotes the right channel.
In left/right justified modes:
1: WS = 0 denotes the left Channel
0: WS = 0 denotes the right channel.
4 FIXED_SCK R RW 0
0: SCK = 16 * WS, 32 * WS or 64 * WS for 8-bit, 16-
bit and 32-bit width, 64 * WS otherwise.
1: SCK = 64 * WS
5MONO R RW0
0: Stereo
1: Mono mode. Read samples from the left channel
and send out on both the channels.
6DMA_MODER RW0
0: Register-based transfers
1: DMA-based transfers
10:8 BIT_WIDTH R RW 1
0: 8-bit
1: 16-bit
2: 18-bit
3: 24-bit
4: 32-bit
5-7: Reserved
12:11 MODE R RW 0
0, 3: I2S Mode
1: Left Justified Mode
2: Right Justified Mode
30 TX_CLEAR R RW 0
0: Do nothing
1: Clear transmit FIFO
Use only when ENABLE=0; behavior undefined
when ENABLE=1
After TX_CLEAR is set, software must wait for
TXL_DONE and TXR_DONE before clearing it.
31 ENABLE R RW 0
Enable the block here only after all the configura-
tion is set. Do not set this bit to 1 while changing
any other value in this register. This bit is synchro-
nized to the core clock.
Setting this bit to 0 completes transmission of the
current sample. When DMA_MODE = 1, the
remaining samples in the pipeline are discarded.
When DMA_MODE=0, no samples are lost.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
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