FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 101
FX3 Serial Peripheral Register Access
9.1.1.2 I2S_STATUS Register
The I2S_STATUS register reports the current status of the I2S master interface.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0TXL_DONEWR 0
Indicates no more data is available for transmis-
sion on left channel. Non sticky.
If DMA_MODE = 0, this is defined as TX FIFO
empty and shift register empty but asserts only
when ENABLE = 0.
If DMA_MODE = 1, this is defined as socket is
EOT and shift register empty.
Note that this field only asserts after a transmis-
sion starts – its power-up state is 0.
1TXL_SPACEWR 1
Indicates space is available in the left TX FIFO.
This bit is updated immediately after writes to
EGRESS_DATA_LEFT register.
Only relevant when DMA_MODE = 0. Non sticky.
2 TXL_HALF W R 1
Indicates that the left TX FIFO is at least half
empty.
This bit can be used to create burst-based inter-
rupts and is updated immediately after writes to
EGRESS_DATA_LEFT register.
Only relevant when DMA_MODE = 0. Non sticky.
3TXR_DONEWR 0
Indicates no more data is available for transmis-
sion on right channel. Non sticky.
If DMA_MODE = 0, this is defined as TX FIFO
empty and shift register empty but asserts only
when ENABLE = 0.
If DMA_MODE = 1, this is defined as socket is
EOT and shift register empty.
Note that this field only asserts after a transmis-
sion was started – its power-up state is 0.
4TXR_SPACEWR 1
Indicates space is available in the right TX FIFO.
This bit is updated immediately after writes to
EGRESS_DATA_LEFT register.
Only relevant when DMA_MODE = 0. Non sticky.
5 TXR_HALF W R 1
Indicates that the right TX FIFO is, at least, half
empty.
This bit can be used to create burst-based inter-
rupts and is updated immediately after writes to
EGRESS_DATA_LEFT register.
Only relevant when DMA_MODE=0. Non sticky.
6PAUSEDWR 0
Output is paused (PAUSE has taken effect). Non
sticky.
7NO_DATAWR 0
No data is currently available for output, but
socket does not indicate empty. Only relevant
when DMA_MODE=1. Non sticky.
8 ERROR RW1S RW1C 0
An internal error has occurred with cause
ERROR_CODE. Must be cleared by software.
Sticky
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