FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 102
FX3 Serial Peripheral Register Access
9.1.1.3 I2S_INTR Register
The I2S_INTR register shows the current state of various interrupts related to the I2S interface. If
any of these interrupts are set and the corresponding interrupt is unmasked through the
I2S_INTR_MASK register, the ARM CPU is interrupted.
27:24 ERROR_CODE W R 0xF
Error code, only relevant when ERROR = 1.
ERROR logs only the FIRST error to occur and
will never change value as long as ERROR = 1.
11: Left TX FIFO/DMA socket underflow
12: Right TX FIFO/DMA socket underflow
13: Write to left TX FIFO when FIFO full
14: Write to right TX FIFO when FIFO full
15: No error
28 BUSY W R 0
Indicates the block is busy transmitting data. This
field may remain asserted after the block is sus-
pended and must be polled before changing any
configuration values.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 TXL_DONE RW1S RW1C 0
Set by hardware when I2S_STATUS.TXL_DONE
assert, cleared by software.
1 TXL_SPACE RW1S RW1C 0
Set by hardware when I2S_STATUS.TXL_SPACE
asserts, cleared by software.
2 TXL_HALF RW1S RW1C 0
Set by hardware when I2S_STATUS.TXL_HALF
asserts, cleared by software.
3 TXR_DONE RW1S RW1C 0
Set by hardware when TXR_DONE asserts,
cleared by software.
4 TXR_SPACE RW1S RW1C 0
Set by hardware when
I2S_STATUS.TXR_SPACE asserts, cleared by
software.
5 TXR_HALF RW1S RW1C 0
Set by hardware when I2S_STATUS.TXR_HALF
asserts, cleared by software.
6 PAUSED RW1S RW1C 0
Set by hardware when I2S_STATUS.PAUSED
asserts, cleared by software.
7 NO_DATA RW1S RW1C 0
Set by hardware when I2S_STATUS.NO_DATA
asserts, cleared by software.
8 ERROR RW1S RW1C 0
Set by hardware when I2S_STATUS.ERROR
asserts, cleared by software.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
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