FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 29
FX3 Overview
Figure 3-6. I2S Blocks
The I2S block can be configured to support different audio bus widths, endianess, number of
channels, and data rate. By default, the interface is protocol standard big endian (most significant bit
first); nevertheless, the block's endianess can be reversed. FX3 also supports the left justified and
right justified variants of the protocol. When the block is enabled in left justified mode, the left
channel audio sample is sent first on the SDA line.
In the mono mode, the 'left data' is sent to both channels on the receiver (WordSelect=Left and
WordSelect=Right). Supported audio sample widths include 8, 16, 18, 24, and 32 bit. In the variable
SCK (Serial Clock) mode, WS (WordSelect) toggles every Nth edge of SCK, where N is the bus
width chosen. In fixed SCK mode, however, WS toggles every thirty-second SCK edge. In this mode,
the audio sample is zero padded to 32 bit. FX3 supports word at a time (SGL_LEFT_DATA,
SGL_RIGHT_DATA) I2S operations for small transfers and DMA based I2S operations for larger
transfers. The Serial Clock can be derived from the internal clock architecture of FX3 or supplied
from outside using a crystal oscillator. Typical frequencies for WS include 8, 16, 32, 44.1, 48, 96, and
192 KHz.
Two special modes of operation, Mute and Pause are supported. When Mute is held asserted, DMA
data is ignored and zeros are transmitted instead. When paused, DMA data flow into the block is
stopped and zeros are transmitted over the interface.
FX3: I2S
Master Tx
External Device:
Slave Receiver
SDA
WS
SCK
PAUSE
MUTE
DMA/SGL TRANSMIT
SGL_LEFT_DATA
SGL_RIGHT_DATA
DMA_LEFT_DATA
DMA_RIGHT_DATA
FIXED/
VAR SCK
INT_CLK
EXT_CLK
CLK_SEL
INT/EXT
STEREO/
MONO
LEFT FIRST
/RIGHT FIRST
AUDIO WIDTH
ENDIANNESS
ENABLE
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