DATA PRECISION 1350 User Manual

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62-5008

MODEL

1350

4.3

SYSTEM

TIMING

Operation

of

the

dual

ramp

integrating

A/D

converter

is

accomplished

in

three

steps

in

each

conversion

cycle.

Programming

control

for

the

cycle

is

developed

in

the

monolithic

IC

from

a

master

timing

circuit

whose

basic

frequency

is

adjusted

so

that

the

conversion

timing

will

result

in

maximum

rejection

of

power-line

correlated

noise

components.

The

three

steps

in

each

AID

conversion

cycle

are:

Step

1:

Autozeroing

Step

2:

Integration

of

Conditioned

Input

Step

3:

Integration

of

Reference

Voltage

In

the

Autozeroing,

Step

1,

which

is

programmed

to

last

100

millisec

onds:

the

analog

section

of

the

converter

is

zeroed

by

closing

the

loop

around

the

components

and

storing

a

compensating

voltage

to

balance

the

no-zero

effects

in

the

loop.

Integration

of

the

Conditioned

Input,

Step

2,

is

programmed

to

last

for

100

milliseconds,

during

which

an

integrating

capacitor

is

charged

to

a

voltage

proportional

to

the

magnitude

of

an

input.

The

precise

interval

of

STEP

1

-W-

MINIMUM

AUTO

ZERO

100

MSEC

INPUT

INTEGRATION

REFERENCE

INTEGRATION

ANDAUTOZERO

FOR

IN:rANGE

INPUTS

100MSEC

200MSEC

NO

EOC

1

APPROX

FULL

-SCALE

(1000

COUNTS)

NEGATIVE

INPUT

2

100%

OVERRANGE

(1999

COUNTS)

NEGATIVE

INPUT

3

OUT-OF-RANGE

(

1999

COUNTS)

NEGATIVE

INPUT

Figure

4-2.

System

Timing

Diagram

©

Copyright

1977.

Data

Praciston

Corporation.

All

righ

4-3

Table of Contents

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DATA PRECISION 1350 Specifications

General

Brand	DATA PRECISION
Model	1350
Category	Multimeter
Language	English