DATA PRECISION 1350 User Manual

62-5008 MODEL 1350
4.4.3 AC/DC Converter Signal Conditioning
When the ac mode of signal conditioning is selected for either voltage or
current measurement, the range-attenuated signal is connected to the
AG/DC converter shown in simplified schematic in Figure 4-5. The invert
ing input to Z1 follows the ac signal input through 011 to the non-inverting
input. The ac signal appears across R26, and is rectified by the operation
of CR9 and CR10 to become a do signal, scaled so that the average value
output of the rectifier is direct reading in rms for sinusoidal inputs.
4.4.4 Resistance Signal Conditioning
As shown in Figure 4-6, the selected voltage source (Hi or Lo) drives the
unknown resistance Rx through a range-selected standard resistance
and a "Posistor" RT1. The voltage developed across Rx is the input to the
A/D in Step 2 (see paragraph 4.3), while the voltage across the selected
standard resistance, produced by the same current as through the
unknown resistance, is the reference input to the AID for Step 3. RT 1
provides protection against large applied voltages by limiting current to
about 10mA.
4.5 A/D CONVERTER DETAILS
4.5.1 Analog Section
The Model 1350 DMM ND converter is a monolithic CMOS 10 containing
both analog and digital sections on one chip. Figure 4-7 illustrates the
analog section, and includes the interfaces with discrete elements on the
main pc-board. As shown in the illustration, the converter consists of a
buffer, integrator, and comparator, configured by internal switches pro
grammed by the digital section. The switches are identified by the step
signals during which they are "ON". For example, the INT switches
are closed during Step 2, Integration of the Conditioned Signal; the A/Z
switches are closed during Step 1, Autozeroing step; the DE switches are
closed during Step 3, Integration of the Reference Signal. Note that the
DE switches are closed in pairs, DE(-i-) when a positive conditioned input
is sensed at the end of Step 2, and DE(-) when a negative conditioned
input is sensed at the end of Step 2.
During Step 1, (A/Z closed), the conditioned input is removed (INT is
open); the AID input is shorted to Analog Common, the integrator/
comparator loop is closed, and capacitor C5 is charged with compensat
ing offsets for automatic zeroing during Steps 2 and 3. Capacitor C4 is
charged with the reference voltage for later use in Step 3.
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-'Copyright 1977. Data Precision Corporation. All rights reserved.

DATA PRECISION 1350 Specifications

General

Brand	DATA PRECISION
Model	1350
Category	Multimeter
Language	English