Dell 1135N - Page 35

Product specification and feature
2-23
Service Manual
■ HVPS Board
• Transfer High Voltage (THV+)
- Input Voltage: 24 V DC ± 15%
- Output Voltage: +1.3KV(Duty Variable)
- Line Regulation : under±3% (fluctuation input 21.6V ~ 27.6V)
- Output Voltage Rising Time 50ms Max
- Output Voltage Falling Time : 100 ms Max
- Fluctuating transfer voltage with environmental various : 0 V~ 5 KV
- Environment Recognition Control Method : The THV-PWM ACTIVE is transfer active signal. It detects the
resistance by recognizing the voltage value, F/B, while permits the environmental recognition voltage.
- Output Voltage Control Method : Transfer Output Voltage is outputted and controlled by changing Duty of
THVPWM Signal.
• Charge Voltage (MHV)
- Input Voltage : 24 V DC ± 15%
- Output Voltage : -1.3KV DC ± 3%
- Output Voltage Rising Time : 50 ms Max
- Output Voltage Falling Time : 50 ms Max
- Output Control Signal(MHV-PWM) : CPU is HV output when PWM is Low
• Cleaning Voltage (THV-)
- -1.2KV ± 15%
- The (+) Transfer Voltage is not outputted because the THV PWM is controlled with high.
- The (-) Transfer Voltage is outputted because the THV-Enable Signal is controlled with low
- The output fluctuation range is big because there is no Feedback control & connection Resistor.
• Developing Voltage (DEV)
- Input Voltage : 24 V DC ± 15%
- Output Voltage: -480V DC ± 3%
- Output Voltage Fluctuation Method : PWM Control
- Line Regulation : under±3% (fluctuation input 21.6V ~ 27.6V)
- Load Regulation : Under ±3%
- Output Voltage Rising Time : 50 ms Max
- Output Voltage Falling Time : 50 ms Max
- Output Control Signal (BIAS-PWM) : the CPU output is HV output when PWM is low.
• Supply
- Output Voltage : -630V DC ± 5% (ZENER using, DEV )
- Line Regulation : under±3% (fluctuation input 21.6V ~ 27.6V)
- Load Regulation : Under ±3%
- Output Voltage Rising Time : 50 ms Max
- Output Voltage Falling Time : 50 ms Max
- Output Control Signal (BIAS-PWM) : the CPU is HV output when PWM is low