Denon DCD-CX3 - Dsd1796 Dbr (Ic105); DSD1796 DBR Block Diagram

41
DCD-CX3
DSD1796DBR (IC105)
30 P32(AIN2) OPEN O
31 P33(AIN3) OPEN O
32 P34(AIN4/STOP2) OPEN O
33 P35(AIN5/STOP3) OPEN O
34 P36(AIN6/STOP4) OPEN O
35 P37(AIN7/STOP5) 3.3V_D4IN I L Watch to +3.3V_D4 (Power at DV3.2)
36 NC OPEN
37 VAREF +3.3V I Power for AD Converter
38 AVDD +3.3V I
39 AVSS GND
40 P40 OPEN O
41 P41 OPEN O
42 P42 OPEN O
43 P43 OPEN O
44 P44 OPEN O
45 P45 OPEN O
46 P46 OPEN O
47 P47 A_Mute1 O L A_Mute STANDBY ; L POWER ON ; HZ
48 NC OPEN
pin No port mode I/O Intial action
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DSDL
DSDR
DBCK
PLRCK
PDATA
PBCK
SCK
DGND
V
DD
MS
MDI
MC
MDO
RST
V
CC
2L
AGND3L
I
OUT
L–
I
OUT
L+
AGND2
V
CC
1
V
COM
L
V
COM
R
I
REF
AGND1
I
OUT
R–
I
OUT
R+
AGND3R
V
CC
2R
System Clock Manager Power Supply
DBCK
DSDL
DSDR
RST
SCK
Advanced
Segment
DAC
Modulator
I
OUT
L+
I
OUT
L–
I
OUT
R–
Current
Segment
DAC
I
OUT
R+
Bias
and
Vref
V
COM
L
V
COM
R
AGND2
V
DD
V
CC
1
V
CC
2L
V
CC
2R
AGND1
I/V and Filter
8
Oversampling
Digital
Filter
and
Function
Control
Audio
Data Input
I/F
PLRCK
PBCK
PDATA
MDO
MDI
MC
MS
AGND3L
AGND3R
DGND
Current
Segment
DAC
I
REF
V
OUT
L
I/V and Filter
V
OUT
R
Function
Control
I/F
DSD1796DBR Block Diagram