Denon DCD-CX3 - DSD1796 DBR Terminal Function; Ba18 Bc0 Fp (Ic803); Ba33 Bc0 Fp (Ic110, 806); Pq033 Rda2 Szh (Ic807)

42
DCD-CX3
DSD1796DBR Terminal Function
BA18BC0FP (IC803)
BA33BC0FP (IC110, 806)
PQ033RDA2SZH (IC807)
TERMINAL
I/O
DESCRIPTIONS
NAME PIN
I/O
DESCRIPTIONS
AGND1 19 – Analog ground (internal bias)
AGND2 24 – Analog ground (internal bias)
AGND3L 27 – Analog ground (L-channel DACFF)
AGND3R 16 – Analog ground (R-channel DACFF)
DBCK 3 I Bit clock input for DSD mode
(1)
DGND 8 – Digital ground
DSDL 1 I/O L-channel audio data input for DSD mode
PCM mode zero flag for L-channel when in zero-flag output mode
(2)
DSDR 2 I/O R-channel audio data input for DSD mode
PCM mode zero flag for R-channel when in zero-flag output mode
(2)
I
OUT
L+ 25 O L-channel analog current output +
I
OUT
L– 26 O L-channel analog current output –
I
OUT
R+ 17 O R-channel analog current output +
I
OUT
R– 18 O R-channel analog current output –
I
REF
20 – Output current reference bias pin
MC 12 I Mode control clock input
(1)
MDI 11 I Mode control data input
(1)
MDO 13 O Mode control readback data output
(3)
MS 10 I/O Mode control chip-select input
(2)
PBCK 6 I Bit clock input for PCM mode
(1)
PDATA 5 I Serial audio data input for PCM mode
(1)
PLRCK 4 I Left and right clock (f
S
) input for PCM mode
(1)
RST 14 I Reset
(1)
SCK 7 I System clock input
(1)
V
CC
1 23 – Analog power supply, 5 V
V
CC
2L 28 – Analog power supply (L-channel DACFF), 5 V
V
CC
2R 15 – Analog power supply (R-channel DACFF), 5 V
V
COM
L 22 – L-channel internal bias decoupling pin
V
COM
R 21 – R-channel internal bias decoupling pin
V
DD
9 – Digital power supply, 3.3 V
(1)
Schmitt-trigger input, 5-V tolerant
(2)
Schmitt-trigger input and output. 5-V tolerant input, and CMOS output
(3)
3-state output
1
FIN
23
Vref
-
+
BLOCK DIAGRAM
Pin Name
Vcc
N.C.
OUT
GND
Pin No.
1
2
3
FIN
TSD
Vcc
(1PIN)
N. C. (2PIN)
OUT
(3PIN)
OCP
R2
R1
Driver
GND(FIN)
1 : DC input (V in)
1
2 : DC output (V o)
2
3 : GND
3
4 : ON/OFF control (V c)
4