Epson RX8130CE - Page 63

19 Serial communication
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ETM50E-07 Seiko Epson Corporation 62
(12) CPU transfers ACK signal for "1".
(13) CPU transfers stop condition [P].
S
(1)
0
R/W
0
(3)
Address
(4)
Sr
(6)
0
(5)
1
R/W
0
(8)
Data
(9)
0
(10)
Data
(11)
P
(13)
1
(12)
ACK from 8130CE
ACK from CPU
(7)
Slave address
(2)
Slave address
3)Read sequence when address is not specified
Once read mode has been initially set, data can be read immediately. In such cases, the address for each read
operation is the previously accessed address + 1.
(1) CPU transfers start condition [S].
(2) CPU transmits the RX8130CE's slave address with the R/W bit set to read mode.
(3) Check for ACK signal from RX8130CE (from this point on, the CPU is the receiver and the RX8130CE is the
transmitter).
(4) Data is output from the RX8130 to the address following the end of the previously accessed address.
(5) CPU transfers ACK signal to RX8130CE.
(6) Repeat (4) and (5) if necessary. Read addresses are automatically incremented in the RX8130.
(7) CPU transfers ACK signal for "1".
(8) CPU transfers stop condition [P].