GE P645

4 CIRCUIT BREAKER FAIL LOGIC
Any Trip
Extern CB1 Trip
1
S
R
Q
T1 IA< Start
&
T1 IB< Start
T1 IC< Start
1
T1 IN< Start
V<1 Trip
V>1 Trip
VN>1 Trip
F>1 Trip
F<1 Trip
CLI1 Trip
RTD 1 Trip
Top Oil >1 Trip
Hot Spot >1 Trip
1
&
S
R
Q
Volt Prot Reset
I< Only
CB Open & I<
Prot Reset & I<
&
1
&
CB1 Closed
&
&
1
1
Trip State
Reset State
Volt Prot Reset
I< Only
CB Open & I<
Prot Reset & I<
&
1
&
Extern CB1 Trip
&
&
1
S
R
Q
Note on SR Latches
All latches are reset dominant and are triggered on the
positive edge. If the edge occurs while the reset is active ,
the detection of the edge is delayed until the reset
becomes non-active.
V00694
Figure 107: Circuit Breaker Fail Logic - part 1
P64x Chapter 10 - CB Fail Protection
P64x-TM-EN-1.3 231