GE P645

The CTS monitors the positive and negative sequence currents of all CTs (2 to 5, depending on the model). A faulty
CT is determined if the following conditions ar
e present at the same time:
● The positive sequence current in at least two current inputs exceeds the set release threshold I1 (CTS I1
setting under the SUPERVISON column). This also means that CTS can only operate if minimum load current
of the protected object is present.
● A high set ratio of negative to positive sequence current, CTS I2/I1>2, is exceeded at one end.
● At all other ends the ratio of negative to positive sequence current is less than a low set value, CTS I2/I1> 1,
or no significant current is present (positive sequence current is below the release threshold I1).
Only a single or double phase CT failure can be detected by this logic. The probability of symmetrical three-phase
CT failures is very low, therefore in practice this is not a significant problem.
3.2 CTS LOGIC
V01227
CT1 I2/I1 > CTS I2/I1>2
&
CT2 I2/I1 > CTS I2/I1>1
CT3 I2/I1 > CTS I2/I1>1
CT4 I2/I1 > CTS I2/I1>1
CT5 I2/I1 > CTS I2/I1>1
&
1
≥2
CT1 I1 > CTS I1
CT2 I1 > CTS I1
CT3 I1 > CTS I1
CT5 I1 > CTS I1
CT4 I1 > CTS I1
Inhibit CTS
Inrush detector
CT Exclusion Alarm
&
&
CT1 Fail
CTS CT1
1
CT Fail alarm
1
& CTS Blk
CT1 I2/I1 > CTS I2/I1>1
&
CT2 I2/I1 > CTS I2/I1>2
CT3 I2/I1 > CTS I2/I1>1
CT4 I2/I1 > CTS I2/I1>1
CT5 I2/I1 > CTS I2/I1>1
&
&
&
CT2 Fail
CTS CT2
CT1 I2/I1 > CTS I2/I1>1
&
CT2 I2/I1 > CTS I2/I1>1
CT3 I2/I1 > CTS I2/I1>2
CT4 I2/I1 > CTS I2/I1>1
CT5 I2/I1 > CTS I2/I1>1
&
&
&
CT3 Fail
CTS CT3
CT1 I2/I1 > CTS I2/I1>1
&
CT2 I2/I1 > CTS I2/I1>1
CT3 I2/I1 > CTS I2/I1>1
CT4 I2/I1 > CTS I2/I1>2
CT5 I2/I1 > CTS I2/I1>1
&
&
&
CT4 Fail
CTS CT4
CT1 I2/I1 > CTS I2/I1>1
&
CT2 I2/I1 > CTS I2/I1>1
CT3 I2/I1 > CTS I2/I1>1
CT4 I2/I1 > CTS I2/I1>1
CT5 I2/I1 > CTS I2/I1>2
&
&
&
CT5 Fail
CTS CT5
CTS Status
Indication
Restrain
1
Figure 134: CTS logic diagram
Chapter 14 - Supervision P64x
292 P64x-TM-EN-1.3