HP 300

To 010
Addr •••
Buffer.
I/o Control
51;"011
I/o Interrupti
010 Interrupt
Un ••
To I/O
Data
Buff,r.
>--
>--
>---
/
"-
I
010 Control
BUI
/r---
010 Addr... BUI
l'
1
I
1 TLB
RAM II I I Lower 010
I
010 Control I
Upper Address Address
Signals
!I
~ I rno ""ff.~ lotohj""".
~ 1 Buffer Control I
RAM Parity
J
~~
r---
t.4t.4U/ORAM
!.H-
.!!.9 0
logical Addr ...
Controller
:5 ~
Control
(t.4CA2800AlS
Physicol Addr ... BUI
~£
u Gate Arroy)
!~ ~
r---
'-r-
e
RAM Control '----
i:f
OD
u:t:
:>
Buffered RAM Control
fl
-
Proc ••• or Data BUI (olio RAM Parity)
I
rest Conector I
Buffer Control
010 Data
Buffers
I
RAM Addr... BUI
1/2 t.4EG
RAM Array
With Pority
1
>----1
'-/
DlO Data
BUI
10 MHZ
/0 -"""" -'"'------r
c~~lfr~~rer
Oisable
wi h
TI CUltom
Chip 1
Addr, .. Decode/
Milc. Signola
tlh
TI CUltom
Chip 2
External
I/O Registers;
Interrupt/t.tisc
Signoll
I/OConlrol8 .. lond
Chip [nobl,SUI
r
+-
I
i
I
I
L
i I
- ------+----------L-J--~~-l
Figure 3-9. 98561-66512 Processor Board Block Diagram
54 Functional Description
l __
1/2 MEG
RAM Array
With Parity
,--
I
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