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HP 5300A - 10 Mhz Oscillator Operation

HP 5300A
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4-21.
The
Al1U4
time
base
is
also
programmed
by
a
83-bit
time
base
code
which
can
select
any
time
base
division
factor
in
powers
of
10,
from
10
to
108.
The
time
base
output
may
also
be
selected
automatically
over
the
same
range.
In
the
auto-ranging
mode
the
range
is
indicated
by
the
number
of
exponent
pulses
generated
by
the
time
base
and
the
control
module.
These
pulses
are
counted,
stored,
and
decoded
by
an
exponent
register
in
the
plug-on
module,
which
then
provides
the
drive
to
the
appropriate
decimal
point
and
units
indicators
in
the
mainframe.
4-22.
The
input
signals
to
the
counter
and
the
time
base
are
routed
through
the
control
module.
For
a
typical
frequency
measurement
as
shown
in
the
block
diagram,
the
F1
input
to
the
counter
is
derived
from
the
input
amplifier
of
the
plug-on
module,
and
the
time
base
input
F2
is
the
reference
frequency
from
the
crystal
oscillator.
In
a
period
average
measure-
ment,
which
is
the
reciprocal
of
frequency,
these
signals
are
reversed.
In
addition
to
the
F2
input,
a
1
MHz
input
to
the
time
base
is
provided
which
by-
passes
the
first
time
base
decade
and
the
control
module
and
allows
auto-ranging
down
to
a
single
cycle
of
the
input
signal.
4-23.
10
MHz
OSCILLATOR
OPERATION
4-24.
The
10
MHz
oscillator
(Figure
8-2)
generates
10
MHz
clock
signals
for
the
5300A
Measuring
Sys-
tem
and
is
plug-ons.
The
oscillator
section
consists
of
U8A,
Y1,
buffer
amplifier
U8B,
and
output
amplifier
Q1.
U8A
operates
as
a
positive
feed-back
amplifier.
The
noninverted
output
maintains
signals
to
10
MHz
crystal
Y1.
4-25.
The
inverted
output
from
U8A
is
sent
through
buffer
amplifier
U8B
and
output
amplifier
Q1.
The
output
from
Q1
connects
through
the
INT-EXT
switch
to
the
input
of
U7A.
The
output
from
U7A
is
sent
to
AlJ1l
where
it
is
available
to
plug-ons
as
the
“CLOCK”
signal.
A
second
output
from
U7A
is
sent
through
U7B
and
the
INT-EXT
switch
to
the
rear-
panel
OSC
jack.
The
OSC
jack
provides
1
volt
rms.
Model
5300A
Theory
of
Operation
4-26.
A1A1
LIGHT
EMITTING
DIODE
ASSEMBLY
(LED)
4-27.
The
display
in
the
5300A
is
a
6-digit,
scanned,
light-emitting-diode
display.
The
display
is
formed
by
a
matrix
of
dots,
each
dot
consisting
of
a
gallium
arsenide
diode
which
emits
red
light
when
current
is
passed
through
it
in
a
forward
direction.
4-28.
Twenty
diodes
are
used
for
each
digit
position,
with
the
diodes
arranged
in
a
4
x
7
matrix
as
shown
in
Figure
4-5A.
For
ease
of
driving,
the
diodes
are
re-
arranged
electrically
into
a
2
x
10
matrix.
4-29.
This
divides
the
digit
into
symmetrical
left
and
right
halves
as
in
Figure
4-5B.
Each
half
digit
has
a
column
drive
line
connected
to
the
anodes
of
all
10
diodes
and
10
cathode
drive
lines
which
are
connected
to
the
same
diode
position
in
every
half
digit.
4-30.
A1U1
SCANNER
4-31.
In
operation
each
half-digit
is
scanned
by
the
circuitry
shown
in
Figure
4-6B.
The
display
is
scanned
from
right
to
left
with
each
half-digit
position
being
driven
for
1/12
the
total
cycle
time.
Integrated
cir-
cuit
U1
generates
the
scanning
sequence
to
drive
the
display
via
12
buffer
drive
transistors,
Q6
to
Q17.
The
scanner
has
a
free-running
internal
clock
whose
fre-
quency
is
set
by
the
external
capacitor
C17.
The
scanning
frequency
is
approximately
10
kHz
so
that
the
complete
display
is
refreshed
in
about
1.2
milli-
seconds.
The
scanner
also
provides
a
four-bit
code
which
identifies
the
half-digit
being
driven.
The
first
bit
identifies
the
right
and
left
hand
halves
of
each
‘digit
and
is
high
when
the
right
hand
half
is
on.
The
other
three
bits,
lines
X, Y,
and
Z,
identify
the
digit
being
displayed.
These
address
the
digit
location
in
the
data
source
which
sends
the
digit
information
as
a
binary
coded
decimal
code
to
the
character
generator,
U2.

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