HP 5300A - 10533 A Digital Recorder Interface Assembly

voltage
becomes
low,
A2Q4
turns
on
through
A2R3
and
A2CR3.
Diode
A2CR3
protects
A2Q4
from
base-
to-emitter
breakdown
in
the
reverse
direction
when
the
battery
voltage
is
high.
4-81.
When
the
battery
voltage
drops
below
11-1/2
to
12
volts,
A2Q4
turns
on.
This
completes
a
path
for
the
+5
volts
from
the
mainframe,
through
A2R5,
and
the
light-emitting
diode
glows.
Normally,
this
occurs
for
a
few
minutes
at
the
beginning
of
a
charge
cycle.
Fuse
Fl
is
in
series
with
the
battery
to
prevent
damage
from
accidental
shorts.
A2CR4
allows
cur-
rent
to
flow
from
the
battery
into
the
mainframe
if
line
power
fails.
A2C2
is
in
parallel
with
the
5300A
filter
capacitor
on
the
unregulated
22
V
line
from
the
5300A
mainframe.
It
provides
additional
filtering
for
the
additional
current
drawn
by
the
batteries
when
the
battery
pack
is
being
used.
For
longest
life
it
is
recommended
that
the
batteries
are
not
continuously
overcharged
for
long
periods
of
time.
Discharging
far
past
the
point
where
the
front
panel
light
comes
on
is
also
undersiderable.
4-82. 10533A DIGITAL RECORDER
INTERFACE ASSEMBLY
NOTE
HP Model 10533A does not work with
5050B unless an Option 050 or 051 is used.
4-83.
The
digital
recorder
output
from
the
5300A
provides
data
in
a
character
serial
format.
The
serial
method
allows
flexibility
in
adapting
to
many
dif-
ferent
serial
or
parallel
output
interfaces.
The
most
common
interface
is
a
standard
parallel
BCD
output
as
used
in
the
HP
5050B
or
5055A
Digital
Recorders.
This
standard
conversion
can
be
obtained
with
the
10533A
Digital
Recorder
Interface
accessory.
The
10533A
accessory
accepts
serial
information
from
the
5300A
and
stores
it
in
parallel
latches
which
drive
the
digital
recorder.
The
units
information
from
the
5300A
is
decoded
in
the
10533A
to
provide
exponent
magnitude
and
sign.
4-84.
Ten
columns
of
information
are
available
to
the
digital
recorder
in
binary-coded-decima!l
form.
Negative
logic
is
used
with
logic
0
about
3
volts
and
logic
1
about
0
volts:
a.
Column
10
(leftmost)
overflow
digit.
An
asterisk
is
presented
when
the
overflow
light
in
the
5300A
display
is
on.
b.
Columns
3
through
9.
Six
digits
of
data
and
the
decimal
point.
The
decimal
point
is
coded
binary
15
and
is
inserted
at
the
correct
position.
On
the
standard
HP
digital
recorder
wheel,
this
is
decoded
and
printed
as
an
asterisk
(*).
Model 5300A
Theory of Operation
ce. Column 2. Exponent sign, either + or -.
Coded binary 10 for +, binary 11 for -.
d. Column 1. Exponent magnitude, either 0, 3,
or 6. The exponent information is coded as follows:
Hz: +0
kHz: +3
MHz: +6
sec: -0
msec: -3
psec: -6
no units: -0
; -3
Le: -6
(These are the only allowable combinations of units
in the 5300A.)
4-85.
Each
column
of
data
is
stored
in
a
4-bit
latch.
The
data
is
scanned
into
the
locations
by
the
outputs
from
the
shift
register,
U1.
The
shift
register
is
scan-
ned
by
the
Data
Clock
and
the
Decimal
Point
Clock
via
the
exclusive-OR
gate,
U2.
The
Decimal
Point
Clock
is
always
delayed
with
respect
to
the
Data
Clock,
by
about
200
nsec,
and
is
high
when
the
Data
Clock
is
low.
Therefore,
the
output
from
the
exclusive
OR
gate
is
a
short
pulse
at
the
beginning
and
after
the
end
of
the
Decimal
Point
Clock.
The
pulse
width
is
equal
to
the
200
nsec
delay
between
the
two
clock
lines.
The
leading
pulse
“clocks”
the
decimal-point-
code
into
the
corresponding
latches
and
the
trailing
pulse
“clocks”
the
data
into
the
next
digit
position.
The
scan
sequence
is
synchronized
with
the
scanning
of
the
5300A
display
by
the
START
DATA
signal
which
inserts
a
low
state
into
the
shift
register.
The
low
state
is
then
scanned
by
the
clock
pulses
through
the
seven
outputs
of
the
shift
register.
4-86.
A
positive
print
command
is
received
and
digit-
ally
delayed
by
U3B.
The
delay
allows
one
complete
scan
cycle
to
occur
and
enter
new
data
into
the
latches.
After
a
delay
of
one-scan
cycle,
a
print
com-
mand
is
sent
from
U3B
to
the
digital
recorder.
If
a
RESET
signal
is
received
the
print
command
to
the
digital
recorder
is
inhibited.
4-87.
The
5300A
may
be
inhibited
from
beginning
a
new
measurement
cycle
by
a
saturated-transistor.
in-
hibit
signal
from
the
digital
recorder.
The
output
from
the
10533A
is
a
50-pin
Amphenol
microribbon
connector
which
mates
directly
with
the
input
con-
nector
of
digital
recorders
such
as
the
HP
5050B
or
HP
5055A.
The
input
to
the
10533A
is
a
20-pin
con-
nector
which
mates
directly
with
the
Ald2
rear-panel
connector
on
the
5300A.
It
is
connected
to
the
plastic
housing
containing
the
logic
module
by
a
6-foot
length
of
screened
cable.
Nonstandard
interface
modules
for
use
with
other
recorder
systems
may
be
obtained
on
special
order
from
Hewlett-Packard.