HP 5300A - Sample Rate

Model
5300A
Theory
of
Operation
Figure 4-9. A1U5 Control Basic Diagram
MANUAL
RESET
FAST
LATCH CHARGE
SAMPLE
b> RATE
M/V
MAX TIME
60
c
of RESET
SCHMITT
TRIGGER
COMPARATORS,
SCHMITT
TRIGGER
SAMPLE
RATE
RESET
INHIBIT
SAMPLE RATE
CONTROL
a
©
9
© RESET
8
Peele ee
F/F
R
les FR O INHIBIT
INHIBIT 17
go EFF
TIMEBASE
QO iNPUT
20 (1oMHZ)
R
TRANSFER
F/F O TRANSFER
V4
Ss
© MGFF
13
O —_——
ee
a 12
SCHMITT
TRIGGER
O COUNTER
5 INPUT
MAIN GATE
TIME BASE
INPUT |
TRANSFER
MGFF ee ee
COUNTER 1
INPUT Lu
which triggers the Sample Rate M.V. The sample
rate capacitor begins charging through the front-panel
SAMPLE RATE control. At a point approximately
halfway up the charging curve the TRANSFER signal
is removed. When the peak charging voltage is
reached, the Reset flip-flop triggers, providing a high
signal at the RESET output. At this point the dis-
charge of the sample rate capacitor is initiated,
having a discharge time of a few milliseconds. Ata
point halfway down the discharge curve, the RESET
signal is removed.
4-10
4-46. At the beginning of the display cycle, the time
base input is gated off by an Inhibit flip-flop. The
INHIBIT signal is removed at the end of the capacitor
discharge. The time base input is then gated on,
beginning a new measurement cycle. An SNHIBIT
signal is available to the plug-on, providing a low.
signal during the display cycle. The displayed infor-
mation may be held indefinitely by switching to the
HOLD position on the front panel. This opens the
charging potentiometer circuits to the sample rate
capacitor and prevents the capacitor from charging up.