HP 5300A - A1 U5 Control Circuit

Medel 5300A
Theory of Operation
Figure 4-8. AlU4 Time Base Basic Block Diagram
BINARY CODE N ——e
SELECTS TIMEBASE
OUTPUT to”
LINE
DECODER
TIME BASE
SELECT CODE
TIMEBASE
OUTPUT
10 MHZ INPUT Tn
LOG
o1
TYPICAL TIME - HSEC
BASE OUTPUT
(SELECT COOE |
BINARY 1)
4-40. A1US CONTROL CIRCUIT
4-41. The signal gating and measurement cycle con-
trol for the 5300A Measuring System is provided by
A1U5 control integrated circuit. Figure 4-9 shows a
basic block diagram. The functions provided are:
gating of signals to the Counter and Time Base,
sample rate control, and provision for RESET and
TRANSFER signals.
4-42. The F] and F2 inputs are shaped by Schmitt-
Triggers and then gated to pins 5 and 20 as the TIME
BASE INPUT and COUNTER INPUT signals. To
maintain optimum drive to the MOS circuits, these
outputs are not routed through the plug-on. During
reset, each output remains in a high state until the
opening of the gates.
CAUTION
Particular care should be taken during servicing
to avoid excessive capacitive loading of these
outputs with probes.
4-43. The Main Gate flip-flop controls gating of the
counted signals. The flip-flop can be set or reset by
low signals at the OPEN (pin 16) or CLOSE (pin 15)
{SELECTED
BY tNPUT
CODE)
'OOusec iON sec 10sec
inputs, or can be triggered by a positive going edge
at the LOG input (pin 14) which comes from the time
base. Following reset, the first LOG input pulse
opens the gate. Subsequent LOG inputs will not
affect the flip-flop until the D input is driven from an
enabling flip-flop which is_set_by the low signal at
either the “9” input or the MAX TIME input. Setting
this flip-flop enables the next LOG pulse to close the
Main Gate and terminate the measurement.
4-44. During manual operation, the MAX TIME
signal enables the closing of the gate at the predeter-
mined gate time. During automatic operation after
the counter has reached 9% of full scale, the “9” input
enables the closing of the gate on the following LOG
pulse, which always occurs before 90% full scale is
reached. The number of LOG pulses occurring while
the main gate is open appears at the EXP output (pin
12). This number of pulses indicates the number of
ranges through which the Time Base has automati-
cally stepped and is used to determine the correct
decimal point and units indication.
4-45. As soon as the main gate closes, a Transfer flip-
flop triggers to provide a low output to transfer data
from the counter to the display. The display cycle is
initiated by the rising edge at the MAX TIME input
4-9