EasyManua.ls Logo

IBM 1 Series - Page 31

IBM 1 Series
198 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
2-20
GA34-0033
i
‘Data
strobe’
is
activated.
The
time
between
‘address
gate
return’
and
‘data
strobe’
activation,
CT2,
is
100
nanoseconds,
minimum,
as
seen
at
the
device
interface.
The
duration
of
‘data
strobe,’
CT3,
as
seen
at
the
device
interface,
is
200
nanoseconds,
minimum.
If
a
parity
error
is
detected
by
the
channel
during
a
read
sequence,
‘data
strobe’
is
not
activated.
‘Data
strobe’
(if
it
has
been
activated)
and
‘address
gate’
are
deactivated
simultaneously
at
the
processor
channel
output.
As
denoted
by
the
relationship
of
CT3
and
CT4
in
Figure
2-8,
‘data
strobe’
may
extend
beyond
the
active
envelope
of
‘address
gate’
by
100
nanoseconds,
maximum,
but
the
overlap
of
‘data
strobe’
and
‘address
gate’
is
100
nanoseconds,
minimum,
as
seen
at
the
device
interface.
Upon
the
deactivation
of
both
‘address
gate’
and
‘data
strobe,’
the
device
deactivates
the
‘condition
code
in
bus’
(and
‘data
bus’
on
read
sequences),
and
‘address
gate
return.’
The
‘condition
code
in
bus’
(and
‘data
bus’
on
read
sequences)
must
be
deactivated
prior
to
the
deactivation
of
‘address
gate
return.’
The
permissible
delay,
T5,
from
the
deactivation
of
both
‘address
gate’
and
‘data
strobe’
to
the
deactivation
of
‘address
gate
return’
is
3
microseconds,
maximum.
This
delay
allows
the
device
attachments
to
generate
additional
strobes,
to
do
additional
resetting,
and
to
accomplish
interlocked
deactivation
with
outbound
logic.
However,
unless
such
functions
are
necessary,
‘address
gate’
should
be
deactivated
as
soon
as
possible
for
performance
reasons.
All
device
actions
for
the
command
must
take
place
before
deactivating
‘address
gate
return.’
The
total
duration
of
the
DPC
sequence
is
timed
out
by
the
channel
for
error-detection
purposes.
The
total
duration
is
measured
as
the
time
from
activation
of
‘address
bus
bit
16’ to
the
deactivation
of
-address
gate
return.’
If
‘address
gate
return’
is
not
deactivated
within
the
time-out,
a
machine
check
occurs
and
the
channel
activates
the
‘halt
or
MCHK’
line.
Under
normal
operation,
if
the
device
attachment
adheres
to
the
specified
times
over
which
it
has
control,
the
total
duration
of
the
sequence
is
within
this
channel
time-out.

Table of Contents

Related product manuals