IBM 1 Series - Page 32

jouueYyD
O/]
Jossss01g
[c-¢
<— Channel time-out p=
Address bus bit 16
|
|
Address bus bits 0—15
Data bus (write)
CT1
|
or4
Address
gate
LVS
|
>
\
|
Tl
|
|
|
Condition
code
in
bus
(1/O
instruction
CC)
!
T4
|
I
|
Data
bus
(read)
|
|
|
CTS
LVS
l
LIS
.
T2
Address
gate
return
|
T5
CT2
|
Data
strobe
:
>
CT3
Key:
Timings:
CT
=channel
times.
8°:
T
= attachment-controlled
times.
0<T1<T2
<3
us
LVS
last
valid
signal,
occurring
in
time,
of
a
group
of
0<T4<TS
<3
us
signals
being
activated
on
the
channel.
The
group
200
ns
<CT1
is
shown
linked
by
short,
dotted
lines
on
the
timing
100
ns
<
CT2
diagram.
|
200
ns
<
CT3
LIS
last
invalid
signal,
occurring
in
time,
of
a
group
of
0
<CTS
<
100
ns
signals
being
deactivated
on
the
channel.
The
group
is
shown
linked
by
short,
dotted
lines
on
the
timing
diagram.
Figure 2-8. DPC sequence timing diagram