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IBM 1 Series - Page 57

IBM 1 Series
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Processor-Initiated
IPL
When
designing
the
IPL
mechanism
for
an
I/O
attachment
device,
there
are
several
important
items
that
must
be
taken
into
consideration.
These
items
can
be
categorized
into
two
groups:
IPL
selection
and
system
reset.
IPL
selection
refers
to
the
ability
of
an
IPL
device
to
be
selected
as
either
being
the
primary
or
the
alternate
loading
device
on
the
channel.
Because
only
the
two
IPL
selected
sources
(plus
host
IPL
function)
are
allowed
on
the
I/O
channel,
the
processor
selects
the
appropriate
device
via
status
bus
bits
0
and
1.
The
device
attachment
must
have
the
capability
of
being
personalized
as
either
primary
or
alternate
or
neither.
Refer
to
Figure
2-19.
Note
that
the
primary
or
alternate selection
is
provided
via
jumpers.
The
processor-initiated
IPL
sequence
consists
of
two
‘system
resets,’
the
second
of
which
performs
a
sequential
timing
function.
With
the
activation
of
the
first
‘system
reset’
and
‘initiate
IPL,’
a
dc
reset
occurs.
This
dc
reset
resets
the
IPL
tag
flip
latch
and
deactivates
the
‘IPL’
tag
from
any
previous
IPL
request,
which
may
have
been
in-process
or
in
a
hung
state.
When
‘system
reset’
deactivates,
the
flip
latch
is
set
and
the
‘IPL’
tag
is
activated.
However,
before
the
flip
latch
changes
state,
due
to delays,
a
logical
O
is
set
into
the
enable
IPL
D-trigger.
Therefore,
IPL
cycle-steal
requests
and
transfers
are
not
yet
enabled.
The
second
‘system
reset’
pulse
becomes
active,
but
does
not
affect
the
IPL
tag
latch
because
the
‘initiate
IPL’
tag
is
inactive.
The
second
‘system
reset’
then
deactivates
and
it
causes
the
active
value
of
the
‘IPL’
tag
to
be
set
in
the
enable
IPL
trigger,
thus
enabling
IPL
requests
and
transfers.
If
a
third
‘system
reset’
occurs,
the
IPL
tag
and
enable
IPL
latches
are
reset.
Device
Reset
For
most
normal
applications,
the
recommended
implementation
to
respond
to
a
Device
Reset
command
(0110
1111;
see
I/O
command
description
in
a
processor
description
manual)
is
to
utilize
the
entire
envelope
of
‘address
gate’
as
a
long
strobe.
This
allows
for
a
greater
length
of
effective
reset
and
for
earlier
clearing
of
logic.
Receiver
Conditioning
Receivers
on
bidirectional
buses
may
have
to
be
conditioned,
depending
on
the
technology
utilized.
This
conditioning
reduces
loading
on
the
particular
bus
to
the
source
that
is
driving
the
bus
at
the
time.
Receiver
conditioning,
by
itself,
serves
no
purpose
as
an
enabling
or
logical
function.
Receiver
conditioning
is
discussed
in
“‘Receiver
Conditioning”
under
‘“Driver/Receiver
Information”
in
this
chapter.
2-46
GA34-0033

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