IBM 1 Series - Page 56

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10sss901g
Sv-C
+ Clock CS
request
(Fig. 2-17)
+Enabled CS
request
+ Clock
interrupt
Clock
| Data
Reset
Poll decision
Cycle-steal
sampling
latch
request ()
(Fig. 2-17)
Clock
Data
+ Enabled ()
interrupt
request
(Fig. 2-17)
+ Interrupt
Reset
CaP
Interrupt
sampling
latch
AND
Inverter inverter
—— Hold
Reset
Data
Q
Polarity
hold
+ No request
AND
+ Poll
level (*)
compare
(Fig. 2-17)
+ Poll
I
+ Poll prime (1)
AND
AND
inverter
Poll capture
Set
CaS
Q
Flip
latch
OR | Reset Q
- Channel resets (e}
(Fig. 2-16)
+ Service gate
return ()
(Fig. 2-16)
- Service gate
capture ()
(Fig. 2-16)
+7
O©O
device interface with channel
off-page
negative active signal
positive shift required
Note: This circuit applies only to devices that do not overlap cycle-steal and interrupts.
Figure 2-18. Poll mechanism—latches
Inverter
DN
OR
+ Poll
propagate
~ Poll return
+Poll capture
(Fig. 2-16)
- Block
requests in
(Fig. 2-17)
Sampling latch (SL)
+ Clock
+ Data
- Reset