IBM 1 Series - Page 55

2-44
GA34-0033
Figure 2-18 shows the poll latches. The sampling latches on the left are
the key to the poll mechanism. The active condition of the ‘poll ID’ bits
for cycle-steal or interrupt cause the respective sampling latches to sample
the state of request and prevent further requests from influencing the
decision to capture for that poll sequence. The designed deskew between
‘poll ID’ and the ‘poll’ tag activation gives these sample latches ample time
to resolve metastability prior to ‘poll’ tag activation. Note that the two
sampling latches are D-triggers without the final output latch. Polarity
holds could be used, but this circuit cannot necessarily be generalized for
use in a multiple-device attachment where cycle-steal requests and
interrupt requests would be processed concurrently.
The two latches on the right side of the figure are common logic in the
poll mechanism, and assume that cycle-steal and interrupt requests are not
posted at the same time. This is the case in a single device adapter. The
poll decision latch is biased to propagate the poll in the absence of a
sampled request. In the absence of ‘poll,’ the poll decision polarity hold
follows the outputs of the sampling latches.. By the time ‘poll’ is activated,
all inputs to the poll decision latch, including the compare of the
interrupting level, are stable. The decision to propagate or capture is,
therefore, made prior to the activation of ‘poll.’ When the ‘poll’ tag is
activated, it holds the value of the poll decision latch and gates the
appropriate ‘poll propagate’ or ‘poll return’ tag. If a decision to capture has
been made, the poll capture latch is also set at this time. A circuit is
provided to block the generation of additional requests-in until the
cycle-steal or interrupt-service sequence is complete. This circuit also
prevents the device from using another asynchronous poll identifier cycle
during the time the ‘+service gate return’ is active.
Figure 2-18 also illustrates the use of resets (‘-channel reset’ line) to
degate tags and accomplish appropriate resetting. Note that Device Reset
is not included in these resets because its action and time of occurrence
are different than the asynchronous channel-directed resets. Device Reset
is a DPC command, and cannot arbitrarily reset the cycle-steal portion of
the poll mechanism and the service gate capture latch. Once a cycle-steal
request has been presented to the interface, the device must follow
through with a dummy service sequence if it receives a Device Reset.
Device Reset affects the interrupt portion of the poll mechanism only
indirectly by resetting the interrupt request at its source. The block
diagram of channel sequence interdependencies (Figure 2-7) shows that an
interrupt-service sequence must follow a poll for interrupt without any
other intervening sequence on the service group. Also, it shows that the
channel cannot concurrently poll for an interrupt during a DPC sequence.
A device can present an interrupt request to the interface and then
withdraw it on execution of a Device Reset or Prepare command.