IBM 1 Series - Page 73

Receiver Conditioning
The number of receivers that can be connected to a bidirectional line is
limited by the total current that the receivers supply to the line, relative to
the amount of current that a driver on the line can sink and still maintain
a down state within specification. These limitations impose a major
restriction to the number of receivers that can be operated by a single
driver. Receiver conditioning relieves these limitations for conventional
technology by providing a means of gating off a receiver when it is not the
intended recipient of the logic signal on the bus. This allows a larger
number of receivers to be connected to the bus. Signals must be provided
to condition the receivers independent of the bus. Conditioning, in itself, is
not an enabling or logical function; however, conditioning signals are
generated from logical conditions in the attachment.
Receiver conditioning is shown in Figure 2-27. When a receiver is not
intended to be responsive to the logic signal on the bus (V,), the control
gate (conditioning driver) holds the second input point of the receiver (V,)
to the lower voltage or down state. Because the bus driver contains a
larger load than the conditioning driver, the conditioning driver is able to
sink more current than the bus driver, thus making V, > V,,. In this state,
current I, is greater than I, and the receiver does not present a current
load as large as it normally would to the bus. Therefore, the receiver is
said to be conditioned off or inactive. It is important to choose a signal
conditioning driver with a low down-level voltage in the region of 0.15
volt or less. Selecting a high-current capability driver and designing for a
low fan-out helps to maintain this low down level.
If the receiver is intended to respond to the logic state on the bus, the
control signal to the conditioning driver releases the appropriate potential
at V,, to allow the receiver to be gated into a state that is responsive to the
logical signal at V,. The receiver is now said to be conditioned on or
active.
The address bus bits 8-15 receivers are conditioned active only with
‘address bus bit 16’ being active. Address bus bits 0O—7 are conditioned
active only during a DPC selection, which is, in effect, ‘address bus bit 16’
being active and a device address comparison. The data bus is conditioned
during: (1) a DPC selection with address bus bit-1 equal to a logical 1 and
only until the deactivation of address gate return, and (2) a service gate
capture for a cycle-steal service sequence for an output transfer and only
until the deactivation of ‘service gate return.’
Note: The receivers must be conditioned active only during the preceding
events; they are to be conditioned off or inactive at all other times.
2-62 GA34-0033