1000BASE-T/100BASE-TX/10BASE-T Physical Layer Compliance Tests Manual
Intel Confidential ix
D.7 10BASE-TX 14_7 Twisted-Pair Model ..............................................................114
E Building and Testing UTP LAN Cables to Insertion Loss Specifications........................115
E.1 Purpose .............................................................................................................115
E.1.1 Network Analyzer Setup and Calibration..............................................115
E.1.2 Measuring the Insertion Loss of the Twisted Pair Cable ......................116
E.2 Alternate Insertion Loss Measurement Techniques ..........................................117
F Reducing Measurement Error by Avoiding Cable Bending ............................................119
G Troubleshooting Guide ...................................................................................................123
G.1 Test Problems ...................................................................................................123
G.1.1 Oscilloscope Setups.............................................................................123
G.1.2 Network Analyzer Setups .....................................................................124
G.2 Conformance Problems.....................................................................................124
G.3 Differential Output Voltage (UTP) (ANSI specification 9.1.2.2) .........................124
G.4 Overshoot (ANSI specification 9.1.3) ................................................................125
G.5 Amplitude Symmetry (ANSI specification 9.1.4)................................................125
G.6 Return Loss (ANSI specifications 9.1.5 and 9.2.2)............................................126
G.7 Rise and Fall Times (ANSI specification 9.1.6) .................................................126
G.8 Open Circuit Inductance (ANSI specification 9.1.7) .......................................... 126
G.9 Duty Cycle Distortion (ANSI specification 9.1.8) ...............................................127
G.10 Transmit Jitter (ANSI specification 9.1.9) ..........................................................128
G.11 Differential Input Signals (ANSI specification 9.2.1)..........................................129
G.12 Receiver Common Mode Rejection (ANSI specification 9.2.3) .........................129
H Manual Register Settings ...............................................................................................131
H.1 82540 and 82546 Families ................................................................................131
H.2 82541 and 82547 Families ................................................................................132
H.3 82544 Family.....................................................................................................132
I 100Base-TX Test Procedure for the 82544 Chip ...........................................................135
I.1 Introduction........................................................................................................135
I.2 Equipment Used for This Procedure .................................................................135
I.3 Specification 9.1.2.2 - Differential Output Voltage (UTP) ..................................136
I.3.1 Test Case .............................................................................................136
I.3.2 Test Purpose ........................................................................................136
I.3.3 Specification .........................................................................................137
I.3.4 Test Equipment ....................................................................................137
I.3.5 Test Fixtures.........................................................................................137
I.3.6 Test Procedure.....................................................................................137
I.4 Specification 9.1.6 - Rise/Fall Times .................................................................140
I.4.1 Test Purpose ........................................................................................140
I.4.2 Specification .........................................................................................140
I.4.3 Test Equipment ....................................................................................140
I.4.4 Test Fixtures.........................................................................................141
I.4.5 Test Procedure.....................................................................................141
I.4.6 Notes for Using Pulse-Width Triggering ...............................................141
I.4.7 10% and 90% of Positive Peak Voltage Calculations .........................146
I.4.8 9.1.6 Rise and Fall Times.....................................................................147
I.5 Specification 9.1.8 - Duty Cycle Distortion (DCD) .............................................148
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