95
Table 51. Port 80h POST Codes
Progress Code Enumeration
0x00,0x01,0x02,0x03,0x04,0x05
Entering S0, S2, S3, S4, or S5 state
Resuming from S2, S3, S4, or S5 state
Early chipset register programming
Exit early platform init driver
Entry to SMBUS execute read/write
Exit SMBUS execute read/write
Detecting presence of memory DIMMs
Override Detected DIMM settings
Crisis Recovery has initiated
Start recovery capsule / valid capsule is found
Begin CPU SMM Init smm relocate bases
Smm relocate bases for APs
Refresh memory space attributes according to MTRRs
Load the microcode if needed
Initialize strings to HII database
continued
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