LaCie 12big Rack Storage Server - POST Code Checkpoints

LaCie 12big Rack Storage Server
User Manual page 76
POST
13.3. POST Code Checkpoints
Table 83 describes the checkpoints that occur during the Power On
Self-Test (POST) portion of the BIOS. These codes are shown on the
motherboard LEDs as described in section 13.1. Introduction. All of
these codes can be seen through the management GUI.
Table 83 - POST Code Checkpoints
Checkpoint Description
3 "Disable NMI, Parity, video for EGA, and DMA
controllers. Initialize BIOS, POST, Runtime
data area. Also initialize BIOS modules on
POST entry and GPNV area. Initialized CMOS
as mentioned in the Kernel Variable ""wC-
MOSFlags.""
4 Check CMOS diagnostic byte to determine
if battery power is OK and CMOS checksum
is OK. Verify CMOS checksum manually by
reading storage area. If the CMOS checksum
is bad, update CMOS with power-on default
values and clear passwords. Initialize status
register A. Initializes data variables that are
based on CMOS setup questions. Initializes
both the 8259 compatible PICs in the system
5 Initializes the interrupt controlling hardware
(generally PIC) and interrupt vector table.
6 "Do R/W test to CH-2 count reg. Initialize
CH-0 as system timer. Install the POSTINT1Ch
handler. Enable IRQ-0 in PIC for system tim-
er interrupt. Traps INT1Ch vector to ""POS-
TINT1ChHandlerBlock.""
8 Initializes the CPU. The BAT test is being done
on KBC. Program the keyboard controller
command byte is being done after Auto detec-
tion of KB/MS using AMI KB-5.
C0 Early CPU Init Start -- Disable Cache - Init Lo-
cal APIC
C1 Set up boot strap processor Information
C2 Set up boot strap processor for POST
C5 Enumerate and set up application processors
C6 Re-enable cache for boot strap processor
C7 Early CPU Init Exit
Checkpoint Description
0A Initializes the 8042 compatible Key Board
Controller.
0B Detects the presence of PS/2 mouse.
0C Detects the presence of Keyboard in KBC port.
0E Testing and initialization of different Input De-
vices. Also, update the Kernel Variables. Traps
the INT09h vector, so that the POST INT09h
handler gets control for IRQ1. Uncompress
all available language, BIOS logo, and Silent
logo modules.
13 Early POST initialization of chipset registers.
24 Uncompress and initialize any platform specific
BIOS modules.
30 Initialize System Management Interrupt.
2A Initializes different devices through DIM. See
DIM Code Checkpoints section of document
for more information.
2C Initializes different devices. Detects and initial-
izes the video adapter installed in the system
that have optional ROMs.
2E Initializes all the output devices.
31 Allocate memory for ADM module and un-
compress it. Give control to ADM module for
initialization. Initialize language and font mod-
ules for ADM. Activate ADM module.
33 Initializes the silent boot module. Set the win-
dow for displaying text information.
37 Displaying sign-on message, CPU information,
setup key message, and any OEM specific in-
formation.
38 Initializes different devices through DIM. See
DIM Code Checkpoints section of document
for more information.
39 Initializes DMAC-1 & DMAC-2.
3A Initialize RTC date/time.
3B Test for total memory installed in the system.
Also, Check for DEL or ESC keys to limit mem-
ory test. Display total memory in the system.