Lexicon 960L - Page 103

Lexicon
7-25
40 PWROK INPUT POWER OK - not used
56 RESET/ INPUT RESET/ - 0 : not used
82 ALL_MUTE/ INPUT ALL MUTE - 0 : forces I2S data to zero(digital mute)
50 CS/ INPUT CHIP SELECT/ - 0 : this slot is being selected, 1 : not selected
47 DS/ INPUT DATA STROBE - data is captured on rising edge of DS/
48 WR/RD INPUT WR/RD - 0 : write operation, 1 : read operation
66 A0 INPUT Address 0 - select which register is written/read to/from (see register
description section)
65 A1 INPUT Not used.
67 D7 BIDIR Data Bus <7> - data is written/read over this bus
68 D6 BIDIR Data Bus <6> - data is written/read over this bus
69 D5 BIDIR Data Bus <5> - data is written/read over this bus
70 D4 BIDIR Data Bus <4> - data is written/read over this bus
79 D3 BIDIR Data Bus <3> - data is written/read over this bus
77 D2 BIDIR Data Bus <2> - data is written/read over this bus
80 D1 BIDIR Data Bus <1> - data is written/read over this bus
81 D0 BIDIR Data Bus <0> - data is written/read over this bus
Clocks
13 TMIX_CKI INPUT TMIX_CKI - master TMIX clock. All local clocks(I2S_FS/, I2S_64FS/,
I2S_256FS) are derived from this clock and TMIX_WCKI. Input frequency
is nominally 24.576Mhz or 22.5792Mhz for 48/96Khz and 44.1/88.2
sample rates respectively.
51 TMIX_CKI/2 INPUT TMIX_CKI/2 - not used
78 TMIX_WCKI INPUT TMIX_WCKI - TMIX word clock. Rising edge denotes start of octal frame.
Input frequency is 44.1Khz or 48Khz.
29 IOBUS_WCLK/ INPUT Not used
35 IOBUS_64FS/ INPUT Not used
57 IOBUS_256FS INPUT Not used
8 I2S_FS/ OUTPUT AD Frame Sync – falling edge denotes start of frame. Locally generated.
37 I2S_64FS/ OUTPUT AD bit clock - falling edge denotes start of bit period. Locally generated.
23 I2S_256FS OUTPUT AD MCLK signal. Locally generated. Does not actually scale with sample
rate. Nominal output frequency is XXXX(44.1/88.2Khz) or
XXXX(48/96Khz)
Pin Name Type Description
Serial Audio
3 I2S0 OUTPUT I2S audio data for channel 1
4 I2S1 OUTPUT I2S audio data for channel 2
5 I2S2 OUTPUT I2S audio data for channel 3
6 I2S3 OUTPUT I2S audio data for channel 4
18 I2S4 OUTPUT I2S audio data for channel 5
19 I2S5 OUTPUT I2S audio data for channel 6
24 I2S6 OUTPUT I2S audio data for channel 7
25 I2S7 OUTPUT I2S audio data for channel 8
20 SDO0 INPUT TMIX Octal data. Received from TMIX2 Octal 0. Octal selection is
determined by the octal select field in the FPGA control register(see
register description for details)
14 SDO1 INPUT TMIX Octal data. Received from TMIX2 Octal 1. Octal selection is
determined by the octal select field in the FPGA control register(see
register description for details)