960L Multi-Channel Digital Effects System Service Manual
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56301 and the Z-80 is also accomplished through this dual port SRAM. Address $7FF in the dual port
SRAM is used to generate an interrupt to the 56301 (DB_MAS_INT0/). The 56301 then reads this address
which is written with interrupt vector data by the Z-80. The interrupt is cleared when this address is read by
the 56301. In a similar fashion, address $7FE in the dual port SRAM is used by the 56301 as an address to
create an interrupt to the Z-80 (MAS_DB_INT0). The description of this page also applies to Z80 #2 and its
associated SRAM shown on sheet 11.
Lexichip #1 (sheet 9)
Lexichip #1 (U40) and its associated DRAM (U41) are shown on sheet 9. Lexichip processes serial digital
audio that is received on the LEXI1_SER_IN signal that is sent from T-MIX #3. Serial digital audio is passed
from Lexichip #1 to Lexichip #2 through the LEXI1_TO_LEXI2_SER signal, and serial audio is returned via
the LEXI2_TO_LEXI1_SER signal. Finally, serial audio is returned after processing to T-MIX #3 on the
LEXI1_SER_OUT signal, completing the audio data path through this group of two Lexichips. Serial audio
is shifted in and out of the Lexichips using the LEXI_256FS clock signal. All four Lexichips receive the
12MHZ clock signal and multiply this clock to 50MHz for internal use using an on-board PLL. The PLL filter
for Lexichip #1 is comprised of R93, R94, and C56. The PLL supply voltage is filtered by R88, C54, and
C22. The DRAM is used by Lexichip to store audio samples for processing. The Z1_DATA bus has
resistors (R65-91) which drive the bus at start-up since all other data bus drivers are tri-stated at this point.
Lexichip #1 and #2 sample the data bus on the rising edge of DBRD_RST0/ to determine the mode in
which they are to be configured.
The Z80-Lexichip Clock GAL (U35) generates the 12MHZ Lexichip clock and the clocks for the Lexichip’s
Z80 interfaces (ZCLKn) as well as the clock for both Z80s (Z80_CLK). This description of this page also
applies to Lexichip #2, #3, and #4 and their associated DRAMs, which are shown on sheets 10, 12, and 13.
I/O Bus Connector (sheet 14)
The Reverb Card passes commands and status between the host Pentium processor and the I/O Bus
peripheral cards through the I/O bus connector (P2).
I/O Bus Control (sheet 15)
The I/O Bus interface is controlled by the 56301 through the circuitry shown on sheet 15. The Lexibus
Control GAL (U20) is configured as a counter that is used by the Lexibus Strobe GAL (U23) to create I/O
Bus data transfer cycles. The I/O Bus control signals consist of an address strobe (IO_AS/), data strobe
(IO_DS/), and read/write qualifier (IO_WR/). (The IO_RD/ signal is no longer used.) Only one of the Reverb
Cards in a 960L can serve as the I/O Bus master, so all control signals are only driven if ENAB_IOBUS/ Is
low, otherwise all I/O Bus outputs from the card are tri-stated. The ENAB_IOBUS/ signal is controlled by the
Pentium host software through the 56301. I/O bus data is transferred through U39, and the I/O Bus address
is driven through U31, U32, and U44. Provisions for a serial EEPROM on the I/O Bus backplane are
supported by the control signals driven through U50. The IOBUS_INT/ shown on U30 is a wire-ored
interrupt signal from the I/O Bus that is not currently used. The Audio Clock Mux (U45) is used to provide
clocks to the T-MIX devices at start-up. The start-up clocks are INIT_CLK and WCLK. After initialization of
the 960L Clock/IO card the TMIX_CKI and TMIX_WCKI signals are active and the mux is switched to use
these clocks for the T-MIX devices.
Startup Sequence
At power-up the 56301 is held in the reset state by the power supply monitor (U37, sheet 1) for a minimum
of 20 ms after +5VD has stabilized. Once the DSP_RESET/ signal has gone high the 56301 will exit the
reset state and read its bootup program from the Boot PROM (U18, sheet 6). If the bootup procedure
completes successfully then the clock measured on R168 will be 80 MHz. If the 56301 failed to boot
correctly this clock will be 3 MHz. After the 56301 has completed its bootup procedure it waits for a startup
program to be sent through the PCI interface. This startup program is sent when the host system is starting
the Windows operating system. If this program is received and executed correctly the DSP LED is
illuminated. Once the 960L application is launched another 56301 program is sent from the host computer.