960L Multi-Channel Digital Effects System Service Manual
7-10
36 XTAL_EN OUTPUT Local oscillator output enable control. When negated, all oscillators are
disabled to reduce signal noise created by the oscillators when not in use.
CPLD Support
15,16,
17
TDI,TCK,TMS INPUT JTAG Interface. Not used except to program the part in place.
30 TDO OUTPUT JTAG Interface. Not used except to program the part in place.
Control Interface
The I/O Clock card appears as two, byte-wide ports on the I/O backplane databus IOBUS_DATA[7:0], at
the addresses determined by the decoding of SLOT_SEL/ and one address bit, IOBUS_ADDR0.
IOBUS_WR/RD determines the direction of data transfer (low=write, high=read), with IOBUS_DS/ being
asserted low during data transfers. U2 captures write data on the rising edge of IOBUS_DS/.
IOBUS_RESET/ and PWROK are used to initialize various internal FPGA state. When low, ALL_MUTE/
forces the octal audio data lines(TMIX1_SERD0,1,2,3,10,11) to zero.
Register Descriptions
OFFSET
ADDR
NAME
Acce
ss
Default
Value
Description
0x00 IDREG(7:0) RO 0x00
Board ID
IDREG(7:4) RO 0 Type(0=IOCLK PCB)
IDREG(3:0) RO 1
Interface revision
0x01 CTLREG(7:0)
CTLREG(7) RW 0 OSC_DRIVES_BNC. Active High. When set, the BNC Output is derived from local 48K
oscillator.(For test purposes only)
The purpose is to loop the BNC OUT to the BNC IN and attempt to lock to it.
This confirms that the BNC input and output paths circuits are functional
CTLREG(6) RW 0 SEL_1X_CLKMODE. Active Low. Set to zero for 44.1/48K, else one for 88.2/96k
CTLREG(5:4) RW 0 WCKSEL(1:0) - System Word Clock Source Select
WCKSEL(1:0) = 0 Selects 48/96 Khz internal oscillator as word clock source
WCKSEL(1:0) = 1 Selects 44.1/88.2Khz internal oscillator as word clock
source
WCKSEL(1:0) = 2 Selects EXT BNC signal as word clock source
WCKSEL(1:0) = 3 Selects IO Backplane SLOT_WCK as word clock source
CTLREG(3) RW 0
Preview Word Clock Select
PVW_WCK_SEL = 0 Selects EXT BNC clock as this board's preview word clock
source
PVW_WCK_SEL = 1 Selects the current SLOT_WCK as this board's preview
word clock source
CTLREG(2) RW 0 PWCLK_EN - Active High. Preview word clock enable. When asserted this board's
selected
preview word clock will be asserted onto the PREVIEW_WCLK pin on the IO Backplane.
Care must be taken so that no more than one PCB on the IO backplane asserts it preview
workclock onto the backplane.
CTLREG(1) RW 1 XTAL_EN. Active High. Enables XTAL Oscillators. This must be asserted to use osc's as
internal clock source.
CTLREG(0) W 0 TESTMODE. Active High. For development purposes only. When enabled, OSC's drive
system clock tree directly, bypassing the PLL.
Clock Bus Interface
All digital audio clocking in the 960L system is derived from U2 and associated on-board circuitry. Clocks
from U2 are buffered by U1 (74FCTT244 or 74ABT244) and driven onto the I/O backplane, which
distributes them to other modules.
To Next Page
Loading...
