Lexicon 960L - FPGA Control Register; FPGA Lock Register

960L Multi-Channel Digital Effects System Service Manual
7-30
BASE+1E0 Crystal AES TX #4
BASE+1C0 Crystal AES TX #3
BASE+1A0 Crystal AES TX #2
BASE+180 Crystal AES TX #1
BASE+160 Crystal AES RX #4
BASE+140 Crystal AES RX #3
BASE+120 Crystal AES RX #2
BASE+100 Crystal AES RX #1
BASE+80 Octal Select Register
BASE+60 Crystal AES TX global chip select (used for synchronized TX reset)
BASE+40 Lock Register
BASE+20 FPGA Control Register
BASE+00 Board I.D. register (read only, hardwired to $33)
FPGA Control Register
Register Bit
Number
Function Active State
7 Bit 1 of encoded source for slot word clock
output
See following
table
6 Bit 0 of encoded source for slot word clock
output
See following
table
5 Bit 1 of encoded source for preview word clock
output
See following
table
4 Bit 0 of encoded source for preview word clock
output
See following
table
3 Slot word clock output enable High
2 Preview word clock output enable High
1 Double speed mode High
0 Local loopback mode (for test only) High
Hex value Selected Word Clock Source
3 AES input #4
2 AES input #3
1 AES input #2
0 AES input #1
FPGA Lock Register
Register Bit
Number
Function Active State
7 (not used) -
6 (not used) -
5 (not used) -
4 (not used) -