Lexicon
7-9
forms most of the interface between the I/O backplane control, data, and clock buses and the on-board
clock generating circuitry.
Pin Name Type Description
Host Interfacse
42 RESET/ INPUT Not used.
33 ALL_MUTE/ OUTPUT Not Used.
39 CS/ INPUT CHIP SELECT/ - 0 : this slot is being selected, 1 : not selected
37 DS/ INPUT DATA STROBE - data is captured on rising edge of DS/
35 WR/RD INPUT WR/RD - 0 : write operation, 1 : read operation
34 A0 INPUT Address 0 - select which register is written/read to/from (see register
description section)
7 D7 BIDIR Data Bus <7> - data is written/read over this bus
8 D6 BIDIR Data Bus <6> - data is written/read over this bus
9 D5 BIDIR Data Bus <5> - data is written/read over this bus
11 D4 BIDIR Data Bus <4> - data is written/read over this bus
12 D3 BIDIR Data Bus <3> - data is written/read over this bus
13 D2 BIDIR Data Bus <2> - data is written/read over this bus
14 D1 BIDIR Data Bus <1> - data is written/read over this bus
18 D0 BIDIR Data Bus <0> - data is written/read over this bus
Clocks
28 BNC_WCLK INPUT External BNC wordclock input
40 SLOT_WCLK INPUT Wordclock from another slot on the IO backplane
25 PLL_512FS INPUT PLL master clock. The frequency of PLL_512FS is 512 times the
TMIX_WCKI rate. Nominally 24.576 or 22.5792Mhz.
29 48K_512FS INPUT Local 24.576Mhz oscillator input
24 44K_512FS INPUT Local 22.5792 Mhz oscillator input
43 TMIX_CKI OUTPUT TMIX_CKI - TMIX master clock.
44 TMIX_CKI/2 OUTPUT TMIX_CKI/2 – A clock that runs at half the rate of TMIX_CKI. All edge
transitions are timed with the falling of of the TMIX_CKI clock.
1 TMIX_WCKI INPUT TMIX_WCKI - TMIX word clock. Rising edge denotes start of an octal
frame. All edge transitions are timed with the falling of the TMIX_CKI
clock.
2 B_256FS OUTPUT A clock signal whose frequency is 256 times the sample rate. All edge
transitions are timed with the falling of the TMIX_CKI clock.
3 B_128FS OUTPUT A clock signal whose frequency is 128 times the sample rate. This signal
is typically used as the I2S bit clock. The falling edge denotes the stqart of
a bit cell. All edge transitions are timed with the falling of the TMIX_CKI
clock.
4 B_64FS/ OUTPUT A clock signal whose frequency is 64 times the sample rate. The falling
edge denotes the start of the word clock period. All edge transitions are
timed with the falling of the TMIX_CKI clock.
5 B_FS/ OUTPUT A clock signal whose frequency is equal to the sample rate. All edge
transitions are timed with the falling of the TMIX_CKI clock.
19 BNC_WCLK_OUT/ OUTPUT A clock signal whose frequency is equal to the sample rate. This signal is
identical to B_FS/, except when OSC_DRIVES_BNC is set in the
CTLREG. All edge transitions are timed with the falling of the TMIX_CKI
clock.
6 PVW_WCLK OUTPUT Preview word clock. This signal, when enabled via the PVWCLK_EN in
the CTLREG, is driven by the BNC_WCLK or the SLOT_WCLK signal.
The selection is determined by the state of the PVW_WCK_SEL field in
the CTLREG.
PLL Signals
22 PUMP_UP OUTPUT VCO pump up signal.
20 PUMP_DN/ OUTPUT Active low, VCO pump down signal
26 LKERRDET OUTPUT PLL Lock error detected signal.
27 PLL_LOCKED INPUT Indicates that the PLL is locked to the selected word clock source. The
state of this can be read from the CPLD CTLREG.
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