Lexicon
7-35
T-MIX #2 (sheet 5)
T-MIX #2 shown on sheet 5 sends serial digital audio to audio output cards on the I/O bus. These digital
audio streams are formatted with eight audio samples per word clock. These audio streams can be probed
on R146-R157, and if a scope is triggered on word clock it is possible to see the audio samples in these
data streams. These signals represent digital audio that has been processed by the Reverb Card, and
when monitored in conjunction with the signals on T-MIX #1 are an indicator of the end-to-end integrity of
the Reverb Card’s audio processing chain. The assignment of these signals to the I/O cards in the system
is under software control and changes depending upon how the I/O bus is populated. The SPO0-7 signals
on the T-MIX are general-purpose I/O pins, which are used to drive the signals DBRD_RST0/ and
DBRD_RST1/. These are the reset signals to the Lexichips.
Gals (sheet 6)
The logic to interface the 56301 to its on-board peripherals is shown on sheet 6. The 56301 Strobe Control
GAL (U19) creates the strobes that interface to the T-MIX control ports (SAMP_RD/, TMIX_WR/,
TMIX_HWEN/). It also generates the sample bus data transceiver control signals (SAMP_RD/ and
SAMP_WR/). The TMIX_HRDY/ signal is used to extend 56301 data transfer cycles as required by the T-
MIX chips. This signal is qualified with the CTRL_SEL/ chip select in this GAL to create the TRANS_ACK/
signal to the 56301. When the TMIX_HRDY/ signal is high and CTRL_SEL/ is low, TRANS_ACK/ is high
and the data transfer cycle is extended.
The 56301 Decode GAL (U17) generates the chip selects for the T-MIX DSP ports (TMIXn_DSP_CS) and it
creates the dual port RAM chip selects, read strobes, and write strobes (DP_RAMn_CS/, DP_RAM_RD/,
and DP_RAM_WR/).
The Tmix Chip Select GAL (U16) generates the T-MIX control port chip selects (TMIXn_CTL_CS/), the Boot
PROM chip select (BOOT_SEL/), and the T-MIX DSP port interface clock (TMIX_DCLK).
The Boot PROM (U18) is used by the 56301 to get its start-up configuration. This information consists of
the 56301 clock PLL multiplier value, which is used to multiply the 6 MHz clock to 80 MHz, and the PCI
subvendor I.D. that is passed to the host Pentium processor as part of the start-up process.
The DSP Interrupt Buffer (U3) is tri-stated at start-up to allow the resistors R36-39 to drive the dual function
interrupt/mode signals to the 56301. When the 56301 senses the rising edge of the DSP_RESET/ signal it
samples the IRQA/, IRQB/, IRQC/, and IRQD/ signals to determine the boot mode it should use. These
resistors set the 56301 to boot from the Boot PROM (U18). After the 56301 is initialized it enables the DSP
Interrupt Buffer using the IRQ_EN/ signal, which passes the interrupt requests to the 56301.
T-MIX #3 (sheet 7)
T-MIX #3 shown on sheet 7 transfers serial digital audio to the four Lexichips on the Reverb Card. These
digital audio streams are formatted with four audio samples per word clock. These audio streams are the
LEXI_n_SER_IN and the LEXI_n_SER_OUT signals. The LEXI_WCLK_IN signal driven from U38 is the
word clock signal for the four Lexichips. The SPO0-7 signals on the T-MIX are general-purpose I/O pins
that are used to drive the signals Z80_INIT1/ and Z80_INIT2/. These are the reset signals to the Z80
microprocessors. The Z80-Lexichip Interface GAL (U26) contains the glue logic to connect the Z80s to the
Lexichips. It generates chip select and memory request signals and also generates the ZWAIT1/ and
ZWAIT2/ signals which are signals that are sent to the Z80s to extend data transfer cycles as required by
the Lexichips.
Z-80 #1 (sheet 8)
Z80 #1 and its associated local SRAM and dual port SRAM are shown on sheet 8. This Z80 (U33) is the
control processor for the Lexichip #1 & #2 reverb engines (U40, U46). Its address and data lines are
connected directly to both the local SRAM and dual port SRAM, and the chip selects for these SRAMs are
generated by Lexichip #1 (DPORT_1_CS/, SRAM1_CS/). The dual port SRAM is initialized with the Z80
start-up code by the 56301 using the port shown on the right-hand side of the chip symbol. The Z80
accesses this SRAM using the port on the left-hand side of the chip symbol. Message passing between the
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